Segmented 3D Nanosheet Channel Isolation for Vertical Transistor Density
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in achieving high transistor density and performance due to limitations in scaling to single-digit nanometer nodes, particularly in maintaining device density and performance with vertically stacked transistors.
Innovation Solution
The method involves forming vertically stacked transistors with multi-channel designs, where the channel regions are oriented to conduct current parallel to the major surface of the chip. This includes forming first and second semiconductor channels with specific gate structures and dielectric layers, and vertically aligning transistors to increase density and reduce minimum spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked transistors are formed to increase transistor density, then device density is improved, but minimum feature distances limit device density and performance
Solution Approach 1:
The patent transitions from planar 2D transistor layout to vertical 3D stacking, where multiple channel regions are stacked vertically along the z-axis. This dimensional change allows transistors to be arranged in three dimensions rather than confined to a two-dimensional plane, thereby increasing transistor density without proportionally reducing minimum feature distances in the lateral directions.
Solution Approach 2:
The transistor structure is segmented into multiple discrete channel regions (first channel region, second channel region, third channel region) stacked vertically. Each channel region can be independently formed and controlled, allowing precise manufacturing of each segment while achieving high overall density through vertical integration.
2Quantity of substance
If planar devices are scaled to single digit nanometer nodes, then transistor density per unit area increases, but scaling challenges limit further density improvement
Solution Approach 1:
The patent addresses scaling limitations by moving from 2D planar scaling to 3D vertical stacking. Instead of continuing to shrink lateral dimensions to increase density, the invention exploits the vertical dimension to accommodate multiple channel regions, thereby achieving higher density without the same degree of lateral scaling complexity.
Solution Approach 2:
Multiple channel regions are nested vertically within a single transistor structure, with each channel region containing source and drain regions. This nested arrangement allows multiple functional elements to be integrated within a compact vertical footprint, increasing effective transistor density without proportionally increasing lateral device complexity.
Data Source
AI summary
Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a first dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with a second dielectric structure. A cavity can be formed between the first sidewalls of the plurality of first and second semiconductor channels. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.