Segmented Vertical NPN Transistor for ESD Filamentation Control
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Solution Overview
Problem
Conventional vertical NPN bipolar transistors experience thermal failure at relatively low currents during longer electrostatic discharge (ESD) pulses due to filamentation, and are not scalable for system-level ESD protection, as they are poor voltage clamps and have limited current handling capabilities.
Innovation Solution
Segmented vertical NPN bipolar transistors are created by cutting the metal and silicide stack of transistor terminal fingers to introduce additional resistance in the lateral current flow path, preventing filamentation and enhancing ESD tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional vertical NPN bipolar transistors use an n+ buried layer and deep n+ sinker diffusion to provide low resistance current return path, then current handling performance is improved for brief ESD pulses, but thermal failure occurs at relatively low currents during longer ESD pulses due to filamentation
Solution Approach 1:
The patent segments the metal and silicide stack of transistor terminal fingers into multiple sections separated by gaps. This segmentation introduces additional resistance in the lateral current flow path, which prevents current filamentation during longer ESD pulses. The gaps in the metal/silicide stack force current to distribute more evenly across the transistor structure, reducing localized thermal stress and preventing thermal failure at lower current levels during extended pulse durations.
2Productivity
If conventional vertical NPN bipolar transistors are designed for brief ESD pulses, then current handling capability is improved, but the device is not scalable for system-level ESD protection at longer pulse lengths
Solution Approach 1:
By segmenting the metal and silicide stacks with gaps, the transistor structure becomes adaptable to longer ESD pulse durations while maintaining current handling capability. The segmentation modifies the current distribution characteristics to prevent filamentation during extended pulses, enabling the device to scale for system-level ESD protection applications where longer pulse lengths are encountered.
Solution Approach 2:
The patent introduces localized gaps in specific regions of the metal and silicide stacks, creating non-uniform resistance distribution. This local modification of structure quality allows the transistor to maintain overall current handling capability while specifically addressing the filamentation issue in the lateral current flow paths, enabling scalability to system-level protection without sacrificing current handling performance.
3Object-affected harmful factors
If conventional vertical NPN bipolar transistors are used as ESD protection devices, then electrostatic discharge protection is provided, but the device is a poor voltage clamp due to voltage fluctuations as a function of current level
Solution Approach 1:
The segmented metal and silicide stack structure modifies the voltage-current characteristics by introducing controlled resistance in the lateral current paths. This segmentation stabilizes the voltage across the transistor during ESD events by preventing current filamentation that causes voltage fluctuations, thereby improving voltage clamp performance while maintaining ESD protection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The segmented design significantly improves the robustness of vertical NPN bipolar transistors during ESD events, particularly at longer pulse lengths, by distributing current evenly and reducing thermal stress, making them suitable for higher performance system-level ESD tests without requiring new photomasked process steps.
Implementation Method 1
cutting the metal and silicide stack of transistor terminal fingers to introduce additional resistance in the lateral current flow path
Implementation Method 2
distributing current evenly and reducing thermal stress
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
In described examples, a segmented bipolar transistor (100) includes a p-base in a semiconductor surface (106) including at least one p-base finger (140) having a base metal/silicide stack including a base metal line that contacts a silicide layer (159) on the semiconductor surface of the p-base finger (140). An n+ buried layer (126) is under the p-base. A collector includes an n+ sinker (115) extending from the semiconductor surface to the n+ buried layer (126) including a collector finger having a collector metal/silicide stack including a collector metal line that contacts a silicide layer on the semiconductor surface of the collector finger. An n+ emitter (150) has at least one emitter finger including an emitter metal/silicide stack that contacts the silicide layer (159) on the semiconductor surface of the emitter finger. The emitter metal/silicide stack and/or collector metal/silicide stack include segmentation with a gap (150c), which cuts a metal line and/or the silicide layer of the stack.