Segmented On-Die Termination for Memory I/O Impedance Matching
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Solution Overview
Problem
High-speed signaling systems with single on-die termination schemes experience sub-optimal performance due to impedance discontinuity and signal attenuation, leading to reduced signaling margins and increased error rates.
Innovation Solution
Implementing multiple, graduated on-die termination structures per high-speed signaling line, allowing for switchable selection between high-load and low-load terminations based on whether the memory module is the destination for incoming signals, thereby optimizing impedance matching and energy absorption without undue signal attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single on-die termination structure is used, then device complexity is reduced, but signaling margins deteriorate due to impedance discontinuity and signal attenuation
Solution Approach 1:
The patent divides the termination structure into multiple segmented elements (first termination element and second termination element) that can be independently controlled. This segmentation allows different portions of the signal path to have different termination characteristics, resolving the contradiction by enabling complex termination behavior through simpler individual elements.
Solution Approach 2:
The patent implements dynamic termination control where the termination elements can be switched between different states (enabled/disabled) based on operational conditions. This dynamic adjustment allows the system to optimize signaling margins for different operating scenarios, resolving the contradiction between simple structure and reliable performance.
2Reliability
If on-die termination is enabled to suppress reflections, then signal integrity improves, but signal attenuation increases leading to reduced signaling margins
Solution Approach 1:
The patent applies different termination characteristics to different locations in the signal path by using multiple termination elements with different controlled impedances. This local differentiation allows optimal termination at reflection-prone locations while maintaining lower attenuation in signal transmission paths, resolving the contradiction between signal integrity and energy loss.
Solution Approach 2:
The patent changes the impedance parameter of termination elements dynamically based on operational mode. By adjusting termination impedance values and enabling/disabling specific elements, the system optimizes the balance between reflection suppression and signal attenuation, resolving the contradiction between signal integrity and energy conservation.
3Ease of operation
If termination control is simplified to single state, then ease of operation improves, but adaptability to different signaling conditions deteriorates
Solution Approach 1:
The patent creates a universal termination control mechanism that can adapt to multiple operating conditions through a single control interface. The termination circuitry can function in different modes (enabled/disabled states) based on control signals, providing versatile adaptation to various signaling conditions while maintaining simple control operation, thus resolving the contradiction between ease of operation and adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signaling margins, reduces bit error rates, and provides additional headroom for increased signaling rates by dynamically adjusting terminations between memory modules.
Implementation Method 1
terminated by resistive loads selected to match the characteristic impedance of the signal lines and thereby cancel undesired reflections
Data Source
AI summary
An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements.