Segmented Overcoat Prevents Cracking During Wafer Polishing

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Solution Overview

Problem

Conventional semiconductor device manufacturing methods often result in overcoat cracking during polishing due to uneven stress distribution, leading to defective devices, especially in power semiconductor devices with thin wafers, as the overcoat fails to protect the interconnection layer and allows water ingress, causing voltage fluctuations.

Innovation Solution

The method involves forming multiple smaller overcoats on both the chip and unavailable regions of the semiconductor wafer, allowing even pressure distribution during polishing and reducing bending stress, thereby preventing overcoat cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a continuous overcoat is formed on the entire wafer surface, then the overcoat provides complete protection to devices, but the overcoat cracks under polishing pressure causing device damage

Engineering Contradiction:
Improveovercoat protection functionVSAvoidovercoat resistance to cracking
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The continuous overcoat is divided into multiple separate overcoat sections, each covering individual devices or device groups. This segmentation allows each section to independently withstand polishing pressure without transmitting stress to adjacent sections, preventing crack propagation while maintaining protective coverage across the entire wafer surface.

Inventive Principle:
Principle #1Segmentation

2Length of moving object

If polishing pressure is applied to thin wafers (200 μm or less), then the wafer thickness requirement is met, but the overcoat sags and cracks under the pressure

Engineering Contradiction:
Improvewafer thicknessVSAvoidovercoat integrity during polishing
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

By dividing the overcoat into discrete sections rather than using a continuous film, the patent enables thin wafers to undergo polishing without overcoat failure. Each segmented section acts as an independent protective element that can accommodate wafer deformation and pressure application without sagging or cracking, thus maintaining manufacturing precision even when achieving the required thin thickness.

Inventive Principle:
Principle #1Segmentation

3Length of moving object

If polishing time is extended to achieve thinner wafer thickness, then the desired thickness is obtained, but the overcoat is more likely to crack due to prolonged stress

Engineering Contradiction:
Improvewafer thicknessVSAvoidpolishing time
Core Design Contradiction:
Length of moving objectVSLoss of time

Solution Approach 1:

The segmented overcoat structure provides enhanced durability during extended polishing operations. Each separate section maintains its structural integrity under prolonged pressure and mechanical stress, allowing the polishing process to continue for the necessary duration to achieve thin wafer thickness without risking overcoat failure, thus resolving the conflict between achieving target thickness and maintaining overcoat integrity over time.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures the overcoat remains intact, preventing damage to the interconnection layer and maintaining device integrity by distributing pressure evenly across the wafer surface, reducing defects and voltage fluctuations.

Implementation Method 1

polishing the back surface of semiconductor wafer while applying pressure by a revolving grinder

Methodology Applied
Scientific EffectAbrasion: Abrasion

Implementation Method 2

mounting the semiconductor wafer upside down on the table with an intervening film, and polishing a back surface of the semiconductor wafer

Methodology Applied
Scientific EffectPressure distribution: Pressure Gradient

Data Source

PatentUS7867829B2Semiconductor device manufacturing method, semiconductor wafer, and semiconductor device
Publication Date: 2011.01.11 MITSUBISHI ELECTRIC CORP
  • US7867829B2 patent drawing
  • US7867829B2 patent drawing
  • US7867829B2 patent drawing

AI summary

There is provided a semiconductor device manufacturing method which prevents cracking of an overcoat during polishing process, and a semiconductor wafer and a semiconductor device which have an overcoat free from cracking. A plurality of divided overcoats 10 are formed on each chip 3 in a chip region 2 and on each unavailable chip pattern in an unavailable region in the periphery of the chips 3 on the surface of a semiconductor wafer 1, and the semiconductor wafer 1 is mounted upside down on a table with an intervening film so that the back surface of the semiconductor wafer 1 is polished.