Power Semiconductor Edge Termination With Segmented Oxide Interface
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Solution Overview
Problem
State-of-the-art power semiconductor devices suffer from high leakage currents and instability under high temperature reverse bias due to the use of undoped polysilicon and SIPOS layers, which have stacking faults and discontinuities at the silicon substrate interface, leading to thermal runaway and reduced breakdown voltage stability.
Innovation Solution
A power semiconductor device design featuring oxide segments and a charge dissipation layer with reduced interface contact area, utilizing SIPOS with controlled oxygen doping and a metal layer to prevent direct contact with the substrate, along with a nitride layer for moisture protection, thereby reducing leakage currents and maintaining breakdown voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If undoped polysilicon or SIPOS layer is used as charge dissipation layer, then voltage stabilisation is achieved, but leakage current increases at high temperatures due to stacking faults and discontinuities at the silicon substrate interface
Solution Approach 1:
The patent divides the charge dissipation layer into multiple segments separated by trenches filled with dielectric material. This segmentation reduces the total interface area between the charge dissipation layer and silicon substrate, thereby reducing leakage current while maintaining voltage stabilisation functionality in each segment
Solution Approach 2:
The patent extracts or removes portions of the charge dissipation layer by forming trenches that extend through the layer, eliminating the harmful interface regions while preserving the beneficial voltage stabilisation properties in the remaining portions
2Object-generated harmful factors
If oxygen concentration in SIPOS is increased to reduce leakage current, then leakage current decreases, but breakdown voltage stability is reduced due to excessive resistivity
Solution Approach 1:
The patent applies different properties to different regions: the charge dissipation layer maintains appropriate oxygen concentration for conductivity in the active regions, while the trench regions provide isolation and the reduced interface area provides leakage current reduction, achieving both goals simultaneously through spatial differentiation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces leakage currents by up to 40% and ensures stable breakdown voltage performance under high temperature reverse bias conditions by minimizing the interface area and optimizing the charge dissipation layer's contact with the substrate.
Implementation Method 1
the charge dissipation layer is in contact with the upper surface of the semiconductor substrate only at a plurality of interface regions
Implementation Method 2
The tunnelling oxide layer passivates the interface between the undoped polysilicon or SIPOS layer and the silicon substrate underneath
Data Source
AI summary
We herein describe a power semiconductor device having a semiconductor substrate including an active region and an edge termination region surrounding the active region, an edge termination structure located in the edge termination region of the semiconductor substrate, and a plurality of oxide segments located over the upper surface of the edge termination region of the semiconductor substrate, where the plurality of oxide segments are laterally spaced from each other. The power semiconductor device also includes a charge dissipation layer located over the upper surface of the edge termination region of the semiconductor substrate and the plurality of oxide segments, such that the charge dissipation layer is in contact with the upper surface of the semiconductor substrate only at a plurality of interface regions, where the interface regions comprise regions of the semiconductor substrate located laterally between adjacent oxide segments.