Segmented Semiconductor Package Structure for Thermal Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages face warping or cracking due to mismatched coefficients of thermal expansion (CTEs) between substrate and semiconductor die materials, leading to damaged electrical connections and reduced reliability, especially in larger packages.
Innovation Solution
The semiconductor package structure incorporates substrate partitions with wiring structures and molding materials, along with stress buffer layers and strategically placed holes in the substrate to manage thermal expansion stresses, ensuring reliable electrical connections and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a relatively large package (50 mm×50 mm or larger) is used, then the electrical connection area and functionality are improved, but the package is highly stressed due to different coefficients of thermal expansion (CTEs) of substrate and semiconductor die materials, leading to warping or cracking
Solution Approach 1:
The substrate is divided into multiple substrate partitions (first substrate partition, second substrate partition, etc.) that are surrounded by molding material. This segmentation allows each partition to independently manage thermal expansion stresses, preventing warping and cracking across the entire large package area while maintaining electrical connections through wiring structures on each partition.
2Adaptability or versatility
If different substrate and semiconductor die materials are used to achieve desired electrical and functional requirements, then the functionality is improved, but the different coefficients of thermal expansion (CTEs) cause high stress during packaging process, leading to warping or cracking
Solution Approach 1:
By dividing the substrate into separate partitions surrounded by molding material, the patent enables the use of different substrate and semiconductor die materials with different CTEs. Each partition can accommodate its specific material组合 without transmitting thermal expansion stresses to other partitions, thus preventing warping and cracking while maintaining material versatility.
3Area of stationary object
If the package size is increased to 50 mm×50 mm or larger, then the electrical connection capacity and functionality are enhanced, but the stress from thermal expansion differences increases, causing warping or cracking that damages electrical connections
Solution Approach 1:
The large package area is divided into multiple substrate partitions surrounded by molding material. This segmentation maintains structural integrity across the large 50 mm×50 mm or larger package by allowing each partition to independently manage thermal expansion, preventing warping and cracking that would otherwise compromise electrical connections.
Solution Approach 2:
The molding material acts as an intermediary between the substrate partitions and the external environment. It surrounds each substrate partition and helps distribute and manage thermal expansion stresses, protecting the structural integrity of the large package while allowing the use of different materials with different CTEs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates thermal expansion-induced stress, maintaining the integrity of electrical connections and enhancing the reliability and lifespan of semiconductor packages, particularly for larger formats.
Implementation Method 1
The semiconductor package may be highly stressed due to the different coefficients of thermal expansion (CTEs) of the various substrate and semiconductor die materials
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.