Segmented Semiconductor Package Structure for Thermal Stress Relief
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Solution Overview
Problem
Semiconductor packages face reliability issues due to thermal stress caused by mismatched coefficients of thermal expansion (CTEs) between substrate and semiconductor die materials, leading to warping or cracking and potential damage to electrical connections, especially in larger packages.
Innovation Solution
The semiconductor package structure incorporates substrate partitions with strategically placed holes and a stress buffer layer made of polymer material to alleviate thermal stress, and uses a frame and underfill layer to compensate for CTE differences, ensuring reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a large semiconductor package is used, then the electrical connection capability is improved, but the thermal stress and warping risk increase due to CTE mismatch
Solution Approach 1:
The substrate is divided into multiple substrate partitions (first substrate partition, second substrate partition, etc.) that are arranged adjacent to each other. Each partition can independently accommodate semiconductor dies and is separated by molding material. This segmentation reduces the overall area of each individual substrate partition, thereby reducing thermal stress and warping risk while maintaining the total package area for electrical connection capability.
Solution Approach 2:
Different substrate partitions can be made of different materials with different coefficients of thermal expansion (CTEs) to match the specific requirements of the semiconductor dies they accommodate. This allows each local region to have optimized thermal properties, reducing thermal stress at the interface between substrate and die while maintaining the overall package functionality.
2Reliability
If different substrate materials with different CTEs are used, then the thermal expansion mismatch is reduced, but the manufacturing complexity increases
Solution Approach 1:
The substrate is segmented into multiple partitions that can be manufactured separately using standard materials and processes, then assembled together. This approach allows each partition to be optimized for specific thermal requirements while maintaining manufacturing simplicity through modular construction.
Solution Approach 2:
The substrate structure uses composite construction with multiple substrate partitions made of different materials, each selected to match the CTE of specific semiconductor dies. The partitions are joined through molding material to create a composite substrate system that achieves thermal compatibility without requiring complex single-material substrates.
3Reliability
If substrate partitions with different thicknesses are used, then the stress distribution is optimized, but the manufacturing precision requirements increase
Solution Approach 1:
The substrate is divided into multiple partitions with different thicknesses (e.g., first substrate partition with first thickness, second substrate partition with second thickness). Each partition can be manufactured to its specific thickness requirement independently, and the segmentation allows for stress optimization without requiring ultra-precise thickness control across the entire substrate.
Solution Approach 2:
Different substrate partitions have different thicknesses tailored to their specific locations and the semiconductor dies they support. This local optimization of thickness allows each region to have optimal stress characteristics while the modular nature of segmentation keeps manufacturing precision requirements manageable through independent fabrication of each partition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the risk of warping and cracking, maintaining the integrity of electrical connections and enhancing the reliability and lifespan of semiconductor packages by managing thermal expansion mismatch.
Implementation Method 1
The semiconductor package may be highly stressed due to the different coefficients of thermal expansion (CTEs) of the various substrate and semiconductor die materials
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.