Segmented Package Wall Structure for Underfill Crack Mitigation
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing smaller package structures for semiconductor devices, particularly in reducing stress-induced cracking of underfill and molding compounds due to the large tensile stress from bonding elements, which affects the performance and reliability of 3D packaging and IC devices.
Innovation Solution
A package structure is developed that includes a semiconductor die bonded to a redistribution structure with a wall structure featuring a plurality of partitions laterally surrounding the die, and an underfill material between the die and the wall structure, which mitigates stress and reduces the risk of cracking by acting as a stress barrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding elements are used to connect semiconductor devices in 3D packaging, then electrical connection and device integration are achieved, but large tensile stress is generated causing cracking of underfill and molding compounds
Solution Approach 1:
The wall structure is divided into multiple partitions that are separated from one another, creating a segmented barrier around the semiconductor die. This segmentation allows stress to be distributed across multiple sections rather than concentrated in a single continuous wall, reducing the likelihood of cracking while maintaining the stress-blocking function.
Solution Approach 2:
The wall structure acts as an intermediary barrier between the bonding elements and the underfill/molding compounds. It intercepts and mitigates the tensile stress generated by bonding elements before the stress can propagate to and crack the underfill and molding compounds, protecting these materials from stress-induced damage.
2Productivity
If package size is reduced to increase production efficiency, then manufacturing cost decreases, but stress concentration increases leading to higher cracking risk
Solution Approach 1:
The wall structure provides localized stress mitigation precisely where needed around the semiconductor die, without requiring a complete increase in package size. By concentrating the stress-blocking function in a targeted wall structure with multiple partitions, the solution maintains small overall package dimensions while providing enhanced local protection against stress-induced cracking.
3Strength
If continuous wall structure is used to surround semiconductor die, then stress barrier effect is maximized, but manufacturing complexity and risk of defects increase
Solution Approach 1:
The wall structure is divided into multiple discrete partitions rather than forming a continuous wall. This segmentation simplifies the manufacturing process by allowing each partition to be formed independently, reducing the complexity of creating a continuous structure while maintaining effective stress barrier functionality through the collective arrangement of multiple partitions.
Solution Approach 2:
Instead of creating a fully continuous wall structure that would maximize stress blocking but increase manufacturing complexity, the invention uses multiple separated partitions that provide sufficient stress mitigation for practical purposes. This partial action approach achieves adequate stress barrier effectiveness without the excessive complexity and defect risk associated with continuous structures.
Data Source
AI summary
A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring. The package structure also includes a substrate on a second surface of the redistribution structure through third bonding elements and in electrical connection with the semiconductor die.