Segmented Phase Change Memory Cell for Tailing Bit Mitigation
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Solution Overview
Problem
Phase change memory cells experience data retention issues and bit errors due to the 'tailing bit' effect, where resistance decreases over time, making it difficult to reliably distinguish between high and low resistance states, and existing solutions like Error Correction Coding (ECC) come with penalties in write efficiency, read speed, and chip size.
Innovation Solution
A memory cell structure with two active regions arranged in series, where bias arrangements induce high and low resistance states in both regions, allowing data storage and retrieval without ECC, ensuring that at least one region remains in a high resistance condition even if one experiences the tailing bit effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Error Correction Coding (ECC) is used to address tailing bit issues, then data retention reliability is improved, but write efficiency deteriorates, read speed deteriorates, and chip size increases
Solution Approach 1:
The memory cell is divided into two separate active regions (first active region and second active region) arranged in series, each capable of independently storing data. This segmentation allows the system to tolerate failures in one region while maintaining data integrity through the other region, thereby improving reliability without requiring ECC overhead that would reduce write efficiency.
2Reliability
If Error Correction Coding (ECC) is used to address tailing bit issues, then data retention reliability is improved, but read speed deteriorates
Solution Approach 1:
By segmenting the memory cell into two active regions in series, the patent enables direct reading of data from either region without requiring complex ECC decoding operations. This maintains fast read speeds while improving reliability, as the segmented structure naturally provides redundancy against tailing bit effects.
3Reliability
If Error Correction Coding (ECC) is used to address tailing bit issues, then data retention reliability is improved, but chip size increases
Solution Approach 1:
The patent segments each memory cell into two active regions, providing inherent redundancy at the cell level rather than requiring additional ECC circuitry at the chip level. This approach improves reliability while minimizing chip size increase, as the redundancy is integrated into the basic memory cell structure itself.
4Device complexity
If a single active region is used in the memory cell, then device complexity is reduced, but data retention reliability deteriorates due to tailing bit effect
Solution Approach 1:
The memory cell is segmented into two active regions arranged in series, which increases structural complexity slightly but dramatically improves data retention reliability. The segmented design ensures that if one region experiences tailing bit effects, the other region maintains the correct resistance state, providing natural redundancy without requiring complex external correction mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the failure rate of memory cells experiencing the tailing bit effect without using ECC, maintaining data integrity and improving storage performance by ensuring a stable resistance margin.
Implementation Method 1
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits.
Implementation Method 2
The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure
Data Source
AI summary
Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.