Segmented Plating Bar for Minimum Kerf Width
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor die substrate panel technologies require a large kerf width between adjoining package outlines due to the need for wide cutting devices to remove plating bars, which wastes space and limits the density of semiconductor packages.
Innovation Solution
A semiconductor die substrate panel with a plating bar configuration that allows for electrical isolation of plated terminals by severing the plating bar at locations along its length, rather than completely removing it, reducing the kerf width between package outlines and enabling a thinner cutting device width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wide cutting device is used to remove plating bars, then electrical isolation of plated terminals is ensured, but kerf width increases and space for semiconductor packages is reduced
Solution Approach 1:
The plating bar is segmented into multiple sections with gaps between them, allowing the cutting device to use a narrower kerf width while still ensuring electrical isolation. The segments are positioned such that the gaps provide the necessary isolation between adjacent plated terminals without requiring a wide cutting path.
Solution Approach 2:
The plating bar is pre-configured with gaps or weakened sections at predetermined locations before the cutting process. This preliminary structuring allows the cutting device to remove only minimal material to achieve electrical isolation, rather than requiring a wide cutting device to remove the entire plating bar in one pass.
2Area of stationary object
If the cutting device width is reduced to minimize kerf width, then more space is available for semiconductor packages, but complete removal of plating bars becomes difficult
Solution Approach 1:
The plating bar structure is divided into segments with gaps between them, allowing a narrow cutting device to remove each segment independently. The gaps are strategically positioned so that the cutting device can access and remove plating material without requiring excessive width, while still achieving complete removal of conductive material between adjacent terminals.
Solution Approach 2:
Instead of attempting to remove the entire plating bar in a single wide cut, the process uses multiple partial removals at segmented locations. The cutting device makes targeted removals at gap positions, which is easier to execute with a narrower device while achieving the same electrical isolation effect.
3Reliability
If plating bars are completely removed to ensure electrical isolation, then terminal isolation is achieved, but large kerf width is required reducing package density
Solution Approach 1:
The plating bar is segmented into discrete sections with gaps between them. This segmentation allows electrical isolation to be achieved by removing only the gap portions rather than the entire plating bar, significantly reducing the kerf width required and increasing the number of packages that can be produced per substrate.
Solution Approach 2:
The plating bar geometry is changed from a continuous structure to a segmented structure with controlled gap widths. This parameter change in the plating bar design allows the cutting device to use a narrower kerf width while still achieving complete electrical isolation, thereby increasing package density without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the kerf width, allowing for increased space on the substrate for additional semiconductor packages, enhancing package yields by converting fractions of package outlines into whole outlines.
Implementation Method 1
A current is supplied to the plating bars 116, which current travels through the plating tails 118, pads 110, through-holes 112 and fingers 106. When the current is delivered, the tails 118, pads 110, through-holes 112 and fingers 106 are electrified and a charge is created at their surface.
Implementation Method 2
In performing the electroplating process, the substrate 100 is immersed in a plating bath including metal ions in an aqueous solution. The metal ions are attracted to the electrified and charged metal areas. In this way, a layer of gold or other plating metal of a desired thickness may be deposited.
Data Source
AI summary
A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.