Segmented PLL Phase Control for Jitter Rejection and Tracking
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Solution Overview
Problem
Existing clock recovery systems face limitations in jitter rejection and bandwidth, leading to poor performance, increased die area, and higher power consumption, particularly in applications requiring clock generation and extraction.
Innovation Solution
A clock circuit with a phase locked loop (PLL) that incorporates a phase rotator and a delay element, controlled by a phase detector, to apply phase shifts and phase delays for integral and proportional control, respectively, effectively decoupling clock recovery from jitter cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL is used for clock recovery, then the system can generate synchronized clock signals, but the jitter rejection and bandwidth performance are limited
Solution Approach 1:
The control signal from the phase detector is segmented into two separate control paths: a proportional control path that directly controls the VCO for high-bandwidth phase tracking, and an integral control path that controls a feedback delay element for jitter cancellation. This segmentation allows independent optimization of both bandwidth and jitter rejection performance without the traditional trade-off.
2Productivity
If the PLL bandwidth is increased to improve tracking, then the jitter rejection capability deteriorates
Solution Approach 1:
The control signal is divided into proportional and integral components that independently control different elements. The proportional path provides wide bandwidth for tracking while the integral path through the feedback delay element provides narrowband jitter filtering, effectively decoupling the bandwidth-jitter rejection trade-off.
Solution Approach 2:
A feedback delay element is introduced as an intermediary component in the integral control path. This delay element acts as a mediator that filters jitter from the feedback signal before it reaches the phase detector, allowing the VCO to be controlled with a wide bandwidth while still achieving effective jitter rejection through the delayed feedback path.
3Reliability
If conventional clock recovery methods are used, then the system can synchronize clocks, but the die area and power consumption increase
Solution Approach 1:
The feedback delay element serves multiple functions: it provides the integral control action for jitter cancellation, acts as a delay element in the feedback path, and enables the decoupling of proportional and integral controls. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall die area.
Solution Approach 2:
The proportional and integral control functions are merged into a unified control architecture where both controls act on the VCO through different paths. This integration allows the system to achieve high-performance clock recovery with fewer discrete components compared to conventional approaches that require separate tracking and jitter cancellation loops.
Data Source
Figure 1A~2A
Figure 1B
Figure 2B
AI summary
Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.