Segmented Fractional-N PLL for Quantization Noise Cancellation
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Solution Overview
Problem
Traditional Integer-N PLLs face limitations in achieving finer frequency resolution without sacrificing bandwidth, power consumption, or increasing layout area, while Fractional-N PLLs introduce quantization noise that limits loop bandwidth and introduces spurs due to non-idealities in sub-phase generation circuits.
Innovation Solution
A segmented Fractional-N PLL architecture that segments sub-phase information into coarse and fine phase components, using a phase interpolator to cancel quantization noise and reduce net phase noise, thereby enhancing PLL performance by separating signal and noise components and minimizing spur levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Fractional-N PLL uses a delta-sigma modulator to control the feedback divider, then finer output frequency resolution is achieved, but quantization noise limits the loop bandwidth
Solution Approach 1:
The feedback divider control is segmented into two independent paths: a coarse control path using a first delta-sigma modulator for integer division ratios, and a fine control path using a second delta-sigma modulator for fractional division ratios. This segmentation allows each modulator to operate independently with optimized bandwidth characteristics, resolving the contradiction between fine frequency resolution and loop bandwidth limitations.
2Speed
If sub-phase generation is used to reduce feedback divider step, then PLL bandwidth requirement is softened, but spurs are introduced due to non-idealities in the sub-phase generation circuit
Solution Approach 1:
The fine frequency adjustment function is extracted from the sub-phase generation circuit and implemented separately using a second delta-sigma modulator controlling a fractional feedback divider. This extraction removes the source of spurs (non-idealities in sub-phase generation) while maintaining the ability to achieve fine frequency resolution, thus reducing spur levels without sacrificing PLL bandwidth.
3Measurement precision
If the reference clock frequency is reduced to achieve finer frequency resolution, then frequency resolution is improved, but the maximum achievable PLL bandwidth is reduced
Solution Approach 1:
The system changes the parameter of feedback divider control from a single reference clock frequency approach to a dual-modulator approach with separate coarse and fine control paths. This allows the use of a higher reference clock frequency (maintaining bandwidth) while achieving fine frequency resolution through the combined action of both delta-sigma modulators controlling the segmented feedback divider.
Data Source
AI summary
A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.