Segmented PLL Phase Tracking for Jitter Rejection and Clock Recovery
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Solution Overview
Problem
Existing phase locked loop (PLL) devices face limitations in reducing jitter and achieving effective clock recovery due to excessive peaking and limited bandwidth, leading to suboptimal performance in clock generation and extraction applications.
Innovation Solution
The proposed solution involves emulating a voltage-controlled oscillator (VCO) in a digital control loop, splitting feedback loop control into proportional and integral paths, using a phase rotator and a digital accumulator for frequency tracking, and a fine digitally controlled delay element for phase tracking, decoupling high bandwidth requirements for phase noise rejection from clock recovery bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL device uses a single feedback loop control mechanism, then the device complexity is low, but the jitter rejection performance is insufficient and excessive peaking occurs
Solution Approach 1:
The feedback loop control is segmented into two independent paths: a proportional control path that processes phase error signals for immediate correction, and an integral control path that accumulates frequency error signals for long-term drift compensation. This segmentation allows each path to be optimized independently, achieving superior jitter rejection without excessive peaking while maintaining manageable device complexity through modular architecture.
2Speed
If the PLL device increases the bandwidth to improve clock recovery, then the clock recovery performance is improved, but the phase noise rejection capability deteriorates due to excessive peaking
Solution Approach 1:
The control mechanism is divided into proportional and integral paths with different bandwidth characteristics. The proportional path operates at higher bandwidth for fast clock recovery, while the integral path operates at lower bandwidth for effective phase noise rejection. This segmentation resolves the contradiction by allowing each path to operate in its optimal bandwidth range without causing excessive peaking.
Solution Approach 2:
The system dynamically adjusts the operating parameters of the proportional and integral controllers based on signal conditions. By changing the gain and bandwidth parameters of each control path according to the detected signal characteristics, the system achieves fast clock recovery when needed while maintaining phase noise rejection capability, avoiding the excessive peaking that occurs with fixed high-bandwidth designs.
3Measurement precision
If the PLL device uses high-order phase tracking with segmented controls, then the jitter rejection and clock recovery performance are enhanced, but the device complexity increases
Solution Approach 1:
The high-order phase tracking is achieved through segmentation of the control mechanism into proportional and integral paths, each handling specific aspects of phase and frequency tracking. This modular segmentation enables high tracking accuracy while keeping the overall device complexity manageable by organizing complex functions into independent, reusable control blocks.
Solution Approach 2:
The segmented proportional and integral control paths serve multiple functions simultaneously: they provide both phase and frequency tracking, enable fast acquisition and steady-state accuracy, and work together to reject various types of jitter. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby managing device complexity while achieving high measurement precision.
Data Source
AI summary
Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.