Segmented Power Metallization for Stress Relief
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Solution Overview
Problem
Thick copper metallization in power semiconductor devices causes severe thermal expansion mismatch with silicon, leading to film stress, wafer or chip bow, and fatigue degradation, which limits area reduction and increases the risk of device failure during temperature changes.
Innovation Solution
A metal bilayer structure comprising a discontinuous metal layer with laterally spaced metal blocks and a thin continuous base metal layer, where the discontinuous layer is thicker than the base layer, forming a heat sink structure that dissipates heat without imparting excessive stress on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thick copper metallization is used to improve heat capacity and current spreading, then thermal performance is improved, but thermal expansion mismatch causes severe film stress and wafer bow
Solution Approach 1:
The copper metallization layer is segmented into an array of laterally spaced copper blocks rather than a continuous thick layer. Each block is surrounded by a dielectric material, creating discrete thermal management zones that reduce cumulative stress while maintaining heat dissipation capability
Solution Approach 2:
The copper blocks are positioned specifically over the power device regions where heat generation occurs, providing localized thermal management. The dielectric material surrounding each block provides local stress isolation, allowing the structure to accommodate thermal expansion locally without transmitting stress across the entire wafer
2Use of energy by moving object
If thick copper metallization is used to improve electro-thermal performance, then energy-density capability is improved, but wafer bow becomes more severe
Solution Approach 1:
The continuous copper layer is divided into discrete blocks separated by dielectric material. This segmentation maintains the thermal mass needed for high energy-density capability while preventing the cumulative stress that causes severe wafer bow in continuous thick copper layers
Solution Approach 2:
A dielectric material is introduced as an intermediary between the copper blocks and the underlying substrate. This dielectric layer acts as a stress buffer that decouples the thermal expansion of copper from the silicon substrate, reducing wafer bow while allowing the copper blocks to maintain high thermal capacity
3Reliability
If thick copper film is used to improve current spreading, then lateral resistance is reduced, but mechanical strength enables thick-copper-wire bonding
Solution Approach 1:
Multiple discrete copper blocks are arranged in an array pattern that provides both current spreading capability and mechanical strength. The blocks are positioned to overlap with wire bond landing zones, allowing thick copper wire bonding to be performed on the mechanically robust block structures while the array configuration maintains low lateral resistance across the device area
4Temperature
If thick copper metallization is used to improve heat dissipation, then thermal performance is improved, but thermal expansion mismatch induces fatigue degradation
Solution Approach 1:
The copper metallization is segmented into discrete blocks surrounded by dielectric material. This segmentation creates isolated thermal expansion zones that cannot transmit stress cycles across the entire structure, dramatically reducing fatigue degradation from repetitive thermal cycling while maintaining effective heat dissipation from each power device region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces bow and fatigue issues while maintaining high thermal performance by minimizing stress and ensuring effective heat dissipation, thereby enhancing the robustness and longevity of power semiconductor devices.
Implementation Method 1
the continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks
Implementation Method 2
the discontinuous metal layer comprises a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.