Segmented Power Transistors for SMPS Ringing Control
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Solution Overview
Problem
Switched mode power supplies (SMPS) face challenges in reducing voltage ringing at the switch node, which causes electromagnetic interference (EMI), while increasing the resistance of power transistors to dampen ringing leads to efficiency losses due to increased power dissipation.
Innovation Solution
Implementing multiple parallel-coupled power transistors with different sizes, where a larger transistor is turned on after a smaller one, to control the gate control signals and manage the switching process, thereby increasing the effective resistance during certain periods to reduce ringing while maintaining efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the resistance of power transistors is increased to dampen voltage ringing, then voltage ringing is reduced, but power dissipation increases leading to efficiency losses
Solution Approach 1:
The power transistor is segmented into multiple parallel-coupled transistors with different sizes (e.g., first transistor with width W1, second transistor with width W2 where W2 > W1). This segmentation allows each transistor to contribute differently to the overall resistance and ringing dampening, enabling fine-grained control of the damping effect while maintaining efficiency.
Solution Approach 2:
Different transistors in the parallel-coupled configuration have different local qualities (different widths/sizes). The larger transistor provides stronger damping capability when needed, while the smaller transistor maintains lower resistance for efficiency. This local quality differentiation resolves the contradiction by allowing the system to exhibit different effective resistance characteristics dynamically.
2Adaptability or versatility
If multiple parallel-coupled transistors with different sizes are used, then ringing control flexibility is improved, but device complexity increases
Solution Approach 1:
Multiple transistors with different functions (damping control and power switching) are merged into a single parallel-coupled configuration. The logic circuit merges the control of multiple transistors into unified gate control signals, simplifying the overall control architecture while maintaining the flexibility of having different transistor sizes for optimized ringing control.
Solution Approach 2:
The system dynamically controls the switching of different-sized transistors based on operating conditions. The logic circuit generates gate control signals that can selectively activate different transistor combinations, allowing the effective resistance and damping characteristics to dynamically adapt to varying voltage and current conditions without requiring complex external control circuitry.
Data Source
AI summary
In at least some examples, an apparatus includes a logic circuit, first transistor, and second transistor. The logic circuit has a first logic circuit output, and a second logic circuit output. The first transistor has a first transistor gate, a first transistor source, and a first transistor drain, the first transistor gate coupled to the first logic circuit output, the first transistor drain adapted to couple to a voltage source, and the first transistor source coupled to a switching terminal. The second transistor has a second transistor gate, a second transistor source, and a second transistor drain, the second transistor gate coupled to the second logic circuit output, the second transistor drain adapted to couple to the voltage source, and the second transistor source coupled to the switching terminal, wherein a transistor width of the second transistor is larger than a transistor width of the first transistor.