Segmented Probe Pad Design for Saw Lane Defect Reduction

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Solution Overview

Problem

During the sawing process of semiconductor wafers containing integrated circuits, metal from metallized structures can cause short circuit defects and cracks in dielectric layers, leading to edge defects in the integrated circuits.

Innovation Solution

The implementation of a semiconductor wafer fabrication method that includes forming segmented probe pad structures in the saw lanes between integrated circuits, with each probe pad structure comprising unsegmented and segmented pads at different interconnect levels, where the pad segments have a maximum lateral dimension up to 75% of the probe pad width, and are electrically connected via vias, to minimize metal interconnect elements and reduce defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If metalized structures such as test components are placed in saw lanes, then electrical testing can be performed on integrated circuits, but metal from these structures causes short circuit defects at edges of the integrated circuits during sawing

Engineering Contradiction:
Improveelectrical testing capabilityVSAvoidshort circuit defect rate
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The probe pad is divided into multiple pad segments separated by dielectric material, creating a segmented structure that reduces metal continuity and minimizes short circuit risks during sawing while preserving electrical testing functionality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Metal interconnect elements are removed or minimized in the saw lane region, extracting the harmful metal component while retaining the essential probe pad functionality through the segmented structure

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If probe pads are placed in saw lanes for testing, then electrical connectivity is established, but cracks and chips in dielectric layers occur during sawing process

Engineering Contradiction:
Improveelectrical connectivityVSAvoiddielectric layer integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The continuous dielectric layer is segmented into multiple dielectric layers separated by metal interconnect elements, creating a stepped configuration that reduces stress concentration and prevents cracks during sawing while maintaining electrical connectivity through vias

Inventive Principle:
Principle #1Segmentation

3Reliability

If continuous metal interconnect elements are used in probe pads, then electrical connectivity is ensured, but metal causes short circuit defects and increased device complexity

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmetal interconnect structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The metal interconnect is segmented into multiple discrete elements separated by dielectric layers, reducing overall metal content and structural complexity while maintaining electrical connectivity through the segmented path with vias

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Excessive metal interconnect elements are removed from the probe pad structure, extracting only the essential conductive paths needed for connectivity while eliminating redundant metal that would increase complexity and defect risk

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9607926B2Probe pad design to reduce saw defects
Publication Date: 2017.03.28 TEXAS INSTRUMENTS INC
  • US9607926B2 patent drawing
  • US9607926B2 patent drawing
  • US9607926B2 patent drawing

AI summary

An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad segments. The pad segments are elements of an interconnect level of the wafer.