Segmented QC-LDPC Decoder for Parallel Low-Latency Decoding
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Solution Overview
Problem
Traditional QC-LDPC decoders in 5G cellular networks face inefficiencies in decoding multiple codewords of varying sizes, leading to high latency and resource-intensive implementations, particularly in handling small codeword sizes for applications like V2X communications.
Innovation Solution
The implementation of a low-latency segmented QC-LDPC decoder configuration that allocates decoding tasks to different segments for parallel processing of multiple message bundles, utilizing a segmented shifter to process edges between check and variable nodes, allowing for efficient and flexible decoding of multiple codewords simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional QC-LDPC decoder processes multiple codewords of varying sizes, then decoding coverage is improved, but decoding latency increases and hardware resources are wasted
Solution Approach 1:
The decoder is divided into multiple processing segments, each capable of independently decoding portions of codewords. This segmentation allows parallel processing of multiple codewords simultaneously, reducing overall decoding latency while maintaining support for varying codeword sizes through flexible segment allocation.
2Adaptability or versatility
If traditional QC-LDPC decoder supports maximum codeword size, then hardware versatility is improved, but hardware efficiency deteriorates for smaller codewords
Solution Approach 1:
The decoder implements dynamic configuration where processing segments can be activated or deactivated based on the actual codeword size being decoded. This dynamic adaptation allows the hardware to efficiently process both maximum-size and smaller codewords by adjusting the number of active segments, eliminating the waste of idle hardware resources.
3Productivity
If multiple instances of decoder logic are used for parallel processing, then throughput is improved, but hardware complexity and resource consumption increase
Solution Approach 1:
Multiple processing segments share common hardware resources including memory structures, control logic, and computational units. This resource sharing approach enables parallel processing of multiple codewords while avoiding the linear increase in hardware complexity that would result from completely separate decoder instances, achieving high throughput with optimized resource utilization.
Data Source
AI summary
Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.