Segmented R-DAC Switch Current Cancellation for Low INL/DNL
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Solution Overview
Problem
High-resolution Digital to Analog Converters (DACs) face challenges with resistor-string architectures due to exponential increases in components, leading to impracticality and issues with power consumption and noise in segmented R-DACs, which compromise monotonicity and complexity.
Innovation Solution
An un-buffered, segmented R-DAC architecture that compensates for resistor ladder loading and reduces output voltage sensitivity through a switch current cancellation scheme, using only resistors and switches, and can be implemented for any resolution and number of segments, with optional 'Truss' and second-order current cancellation architectures to minimize Integral and Differential Non-Linearity errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If segmented R-DAC architecture is used to reduce the number of resistors, then device complexity is reduced, but buffer elements are required which increase power consumption and noise
Solution Approach 1:
The patent removes the buffer elements from the segmented R-DAC architecture entirely. By directly connecting the resistor segments without intermediate buffer amplifiers, the design extracts the harmful power-consuming and noise-generating components while maintaining the segmented structure's advantage of reduced resistor count.
Solution Approach 2:
The patent merges the functions of multiple segments by directly connecting them in series without buffer amplifiers. The segments are combined into a single continuous resistor string where the output is taken from the junction point, eliminating the need for separate buffer amplifiers for each segment.
2Device complexity
If segmented R-DAC architecture is used, then device complexity is reduced, but buffer elements are required which are a major source of noise
Solution Approach 1:
The patent removes the buffer elements from the segmented R-DAC architecture entirely. By directly connecting the resistor segments without intermediate buffer amplifiers, the design extracts the harmful power-consuming and noise-generating components while maintaining the segmented structure's advantage of reduced resistor count.
3Reliability
If buffer elements are added to segmented R-DAC, then resistor ladder loading is alleviated, but power consumption and noise increase
Solution Approach 1:
The patent removes the buffer elements from the segmented R-DAC architecture entirely. By directly connecting the resistor segments without intermediate buffer amplifiers, the design extracts the harmful power-consuming and noise-generating components while maintaining the segmented structure's advantage of reduced resistor count.
Solution Approach 2:
The patent employs a feedback mechanism where the output of one segment is fed back to adjust the loading on the resistor ladder. This feedback control allows the system to maintain proper loading conditions without requiring additional buffer amplifiers, thus avoiding the power consumption and noise penalties.
4Measurement precision
If more resistors are used for high-resolution DAC, then conversion precision is improved, but device complexity increases exponentially
Solution Approach 1:
The patent divides the high-resolution DAC into multiple lower-resolution segments. Each segment handles a portion of the total resolution requirement, and the segments are combined to achieve the overall high-resolution conversion. This segmentation reduces the number of resistors in each individual segment while maintaining the total resolution through the combination of segments.
Data Source
AI summary
An resistor string digital-to-analog converter (DAC) that includes elements to compensate for resistor ladder loading, and/or to provide compensation for loading such as via switch current cancellation. The approach reduces output voltage sensitivity to switch resistances while also reducing INL and DNL errors. Additional resistor loops are optionally disposed at the top and bottom of one or more further segments to provide Nth order resistive current cancellation.