Segmented R-2R DAC Architecture for High-SNR Conversion
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Solution Overview
Problem
Existing high-resolution digital-to-analog converters (DACs) struggle to achieve a signal-to-noise ratio (SNR) above 160 dB/VHz, particularly in dynamic operations, and existing methods to extend resolution are cumbersome or limited by differential linearity defects.
Innovation Solution
A digital-to-analog conversion device comprising a first and second R-2R network DACs, an attenuator, an adder, and a glitch suppression circuit, where the second DAC subdivides the quantization steps of the first DAC, and a filtering circuit minimizes noise, allowing for improved SNR through reduced quantization and differential linearity noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single high-resolution DAC is used, then conversion precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent divides a high-resolution N-bit conversion task into multiple lower-resolution DACs (first DAC with N1 bits, second DAC with N2 bits where N1 > N2). The digital-to-analog conversion function is segmented across multiple devices, each handling different bit ranges, thereby reducing the complexity and cost of individual DAC components while maintaining overall high conversion precision.
Solution Approach 2:
The patent introduces a temporal dimension by sequentially switching between multiple DACs based on the most significant bit (MSB) position. Instead of using one high-resolution DAC for all conversions, the system switches between DACs in different time slots, effectively trading temporal complexity for reduced spatial/device complexity.
2Device complexity
If multiple DACs are used to reduce complexity, then signal/noise ratio deteriorates due to switching transients
Solution Approach 1:
The patent applies preliminary action by pre-charging the holding capacitors of all DACs to the reference voltage level before switching occurs. This pre-charging operation eliminates switching transients and prevents signal perturbations, thereby maintaining high signal-to-noise ratio while enabling rapid switching between multiple DACs.
Solution Approach 2:
The patent implements beforehand cushioning by using a buffer amplifier stage between the DAC outputs and the summing junction. This buffer amplifier isolates the switching DACs from the high-impedance summing node, cushioning against voltage fluctuations and transient effects that would otherwise degrade the signal quality.
3Speed
If DAC switching is implemented, then conversion speed is improved, but linearity accuracy deteriorates due to differential non-linearity
Solution Approach 1:
The patent implements feedback by using a correction DAC that compensates for the differential non-linearity (DNL) errors introduced by the primary DACs. The system measures or characterizes the DNL errors and applies corrective voltage adjustments through the correction DAC, thereby restoring linearity accuracy while maintaining the high conversion speed enabled by DAC switching.
Solution Approach 2:
The patent changes the operating parameters of the DACs by dynamically adjusting the reference voltage levels and switching timing based on the MSB position. By optimizing the voltage ranges and switching sequences, the system minimizes the impact of DNL errors while maintaining high conversion speed.
Data Source
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AI summary
A digital-to-analog converter (DAC) device (100) comprising: - R-2R lattice DACs (102, 104) with resolutions N1 and N2 such that N1 > N2; - an attenuator (106) at the output of the second DAC; - an adder (108) that adds the outputs of the first DAC and the attenuator; - a digital driver circuit (112) that delivers to the input of the first DAC N1 the most significant bits out of N bits to be converted, and to the input of the second DAC (N - N1) other bits, with N2 ≥ (N - N1); - a voltage reference generation circuit (116) coupled to a filtering circuit (114) and delivering a filtered voltage reference to the first DAC; and wherein the quantum qtotal of the device is such that: qtotal <DNLcrête23q1 avec q1 le quantum du premier CNA et DNLcrête la valeur crête des défauts différentiels de linéarité du premier CNA.