Segmented R2R DAC Trim Architecture for DNL and INL Correction
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Solution Overview
Problem
Digital-to-analog converters (DACs) face challenges in achieving accurate output voltage due to errors such as differential nonlinearity (DNL) and integral nonlinearity (INL), which affect their performance and require complex correction mechanisms.
Innovation Solution
A segmented R2R DAC architecture with digitally controlled trim, utilizing MSB, LSB, and binary arm resistors, along with thermometric arm resistors, to generate output voltage and correct DNL errors, allowing for precise voltage adjustments through a controller that maps input codes to output codes to achieve ideal output voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex correction mechanisms are used to reduce DNL and INL errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The DAC uses its own binary arm resistors to generate trim voltages that automatically compensate for DNL errors. The system self-corrects by utilizing the inherent structure of the R2R ladder, where binary arm resistors connected to MSB connector resistors create trim voltages that offset measurement errors without requiring external correction circuits.
Solution Approach 2:
The binary arm resistors serve dual functions: they are integral components of the R2R ladder structure for normal DAC operation, and simultaneously function as trim elements for error correction. This multi-functionality eliminates the need for separate correction circuits, reducing device complexity while maintaining high measurement precision.
2Measurement precision
If additional correction circuits are added to reduce INL error, then measurement precision is improved, but device complexity and area increase
Solution Approach 1:
The patent extracts the error correction function from separate correction circuits and integrates it directly into the existing R2R ladder structure. By taking out the correction functionality and embedding it within the binary arm resistors and their connection to MSB connector resistors, the design achieves INL error reduction without adding external correction circuits.
Solution Approach 2:
The correction circuit functionality is merged with the R2R ladder structure itself. The binary arm resistors are combined with MSB connector resistors to form an integrated trim mechanism that simultaneously performs DAC conversion and error correction, eliminating the need for separate correction circuits and reducing overall device complexity.
3Measurement precision
If high bit resolution is implemented, then measurement precision is improved, but device area and complexity increase
Solution Approach 1:
The DAC architecture segments the resistor network into distinct functional groups: MSB connector resistors, LSB connector resistors, and binary arm resistors. This segmentation allows high bit resolution to be achieved by systematically organizing resistors into hierarchical groups, where each group handles specific bit ranges, thereby managing device area and complexity through structured division rather than monolithic design.
Data Source
AI summary
In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R−ΔR, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.