Segmented Ramp A/D Converter for Low Power Imaging
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Solution Overview
Problem
Conventional solid-state imaging devices face challenges in efficiently converting analog signals to digital signals due to the limitations of single-slope A/D conversion circuits, particularly in terms of noise removal and power consumption, especially when dealing with varying analog signal potentials.
Innovation Solution
The proposed solution involves dividing the ramp period into multiple divided ramp periods, allowing the counter to count time within specific periods, which reduces the number of bits required for the counter and decreases power consumption, while maintaining accurate digital signal output through the use of a decoder that corrects the digital value using offset values based on stop signal values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-slope A/D conversion circuit is used to convert analog signals to digital signals, then the conversion can be performed with a simple circuit structure, but the power consumption increases and noise removal capability is insufficient when dealing with varying analog signal potentials
Solution Approach 1:
The ramp period is divided into multiple divided ramp periods, and the A/D conversion is performed segmentally. This segmentation allows the counter to operate over a shorter time range in each divided period, reducing the number of bits required and thereby lowering power consumption while maintaining conversion accuracy through sequential processing
2Use of energy by moving object
If the ramp period is divided into multiple divided ramp periods and counting is performed in specific periods, then the number of bits required for the counter is reduced and power consumption decreases, but the circuit requires additional control mechanisms
Solution Approach 1:
The circuit pre-determines which divided ramp period will contain the comparison result based on the analog signal potential range. This preliminary action allows the count control circuit to activate only the necessary counter, avoiding the need for complex real-time decision-making mechanisms while reducing power consumption
Data Source
AI summary
An analog/digital converter includes: a ramp signal generation circuit that generates a ramp signal; a comparison circuit that compares potential of an input analog signal with potential of the ramp signal and outputs a comparator output signal if the potential of the ramp signal satisfies the predetermined condition; a count control circuit that divides a predetermined ramp period in which the ramp signal generation circuit outputs the ramp signal into a predetermined number n of divided ramp periods and outputs a count-stop signal; a counter circuit that counts time in the divided ramp period and outputs a count value of the counted time; and a decoder circuit that generates a digital signal according to a count value and a digital value corresponding to any one of the divided ramp periods in which the counter circuit has started counting of time and outputs the generated digital signal.