Segmented Ramp Circuits for Accurate Zero-Crossing Sampling

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Solution Overview

Problem

Sample-data circuits face challenges in maintaining accurate output voltage at the virtual ground node due to delays and noise, which affect performance parameters like speed, accuracy, and power consumption, especially under low power supply voltages and device gain limitations.

Innovation Solution

A zero-crossing detector-based circuit is introduced, utilizing a waveform generator to produce ramp waveforms with varying slopes, controlled by a zero crossing detector to ensure accurate sampling of output voltage, thereby minimizing errors caused by delays and optimizing performance parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If operational amplifier is designed to provide sufficient open-loop gain and fast settling time for accurate integration, then output voltage accuracy is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improveoutput voltage accuracyVSAvoidoperational amplifier design complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the integration function into two parts: a simple switched-capacitor integrator and a separate ramp generator with zero-crossing detector. This divides the complex operational amplifier requirements into simpler components, where the integrator only needs basic switching and the ramp generator handles the voltage level maintenance, reducing overall device complexity while maintaining accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a ramp generator as an intermediary component that produces a controlled voltage ramp to maintain the virtual ground node at the correct level. This intermediary handles the complex voltage control function, allowing the main integrator to operate with simpler operational requirements, thereby reducing device complexity while preserving output accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If operational amplifier is designed for fast settling time, then integration speed is improved, but power consumption increases

Engineering Contradiction:
Improveintegration speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent segments the speed-critical function into the ramp generator and zero-crossing detector, which operate with simple switching and comparison. The main integrator can use a lower-power operational amplifier since it doesn't need to settle as quickly, as the ramp generator actively maintains the virtual ground level, thereby reducing overall power consumption while maintaining integration speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic clocked switching in the switched-capacitor integrator and periodic ramp generation, where the ramp is generated and reset in periodic cycles synchronized with the sampling clock. This periodic operation allows the system to achieve fast effective settling at critical moments while consuming less average power compared to continuous high-speed operation.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If voltage at virtual ground node is maintained precisely at ground all the time, then output voltage accuracy is improved, but power consumption increases

Engineering Contradiction:
Improveoutput voltage accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent uses preliminary action by pre-generating a ramp voltage that proactively maintains the virtual ground node at the correct level before sampling occurs. The ramp generator starts the voltage adjustment in advance and continues it through the sampling phase, ensuring accuracy is maintained precisely when needed without requiring continuous high-power operation throughout the entire cycle.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic maintenance of the virtual ground node voltage using clock-synchronized ramp generation. The ramp is actively maintained during the sampling phase when accuracy is critical, and can be reset or reduced during non-critical phases, thereby maintaining output voltage accuracy while reducing average power consumption compared to continuous maintenance.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP1962292B1Constant slope ramp circuits for sample-data circuits
Publication Date: 2013.04.24 CAMBRIDGE ANALOG TECHNOLOGIES INC
  • EP1962292B1 patent drawingFigure 1
  • EP1962292B1 patent drawingFigure 2
  • EP1962292B1 patent drawingFigure 3

AI summary

A sample-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. A multiple segment ramp waveform generator is used in the sample-data analog circuits. The ramp waveform generator includes an amplifier, a variable current source, and a voltage detection circuit coupled to the current source to control the change in the amplitude of the current. The ramp generator produces constant slope within each segment regardless of the load condition. The sample-data analog circuit also utilizes variable bandwidths and thresholds.