Segmented Row Redundancy Refresh to Cut Memory Power Waste
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Solution Overview
Problem
Existing semiconductor memory devices face issues of unnecessary power consumption and reduced redundancy efficiency during refresh operations due to the activation of defective word lines, which are not addressed by current redundancy determination circuits.
Innovation Solution
The semiconductor memory device is configured with a memory cell array divided into segments, each containing normal and redundant word lines, and a row redundancy circuit that activates non-defective lines during refresh operations, avoiding activation of defective lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more word lines are activated simultaneously during refresh operation to reduce refresh cycles, then productivity is improved, but power consumption increases due to unnecessary activation of defective word lines
Solution Approach 1:
The memory cell array is divided into multiple segments, with each segment containing normal word lines and redundant word lines. The row redundancy circuit operates independently on each segment, activating only non-defective word lines in each segment during refresh operations. This segmentation prevents unnecessary activation of defective word lines across the entire array, reducing power consumption while maintaining refresh efficiency.
Solution Approach 2:
The row redundancy circuit applies different activation strategies to different segments based on their defect status. In segments with defective word lines, the circuit selectively activates only non-defective word lines, while in segments without defects, all word lines can be activated. This local differentiation optimizes power consumption while maintaining overall productivity.
2Reliability
If redundant memory cells are activated to replace defective cells, then reliability is improved, but redundancy efficiency decreases when multiple blocks are involved
Solution Approach 1:
The memory array is segmented into multiple independent regions, each with its own normal and redundant word lines. The row redundancy circuit manages each segment independently, allowing defective word lines in one segment to be replaced by redundant word lines in the same segment without affecting other segments. This independent segment management maintains redundancy efficiency even when multiple blocks are involved.
Solution Approach 2:
The row redundancy circuit acts as an intermediary between the control circuit and the memory cell array segments. It receives control signals, determines which word lines are defective, and selectively activates appropriate redundant word lines in each segment. This intermediary function ensures that redundancy operations are performed efficiently without unnecessary activation of word lines in other segments.
Data Source
AI summary
Provided are a semiconductor memory device, a row redundancy circuit, and a control method of the semiconductor memory device for suppressing unnecessary power consumption. The semiconductor memory device includes a memory cell array and a row redundancy circuit. The memory cell array has a plurality of segments, each segment having a plurality of normal word lines and redundant word lines. The row redundancy circuit is configured to activate non-defective normal word lines and non-defective redundant word lines during a refresh operation. Activation and replacement of defective normal word lines and defective redundant word lines are not performed in each segment during the refresh operation.