Segmented Weighting Resistor Circuit for High-Resolution DACs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital-to-analog converters (DACs) based on resistors require a large range of resistor values, leading to a large physical dimension and increased parasitic nodes, which alter the dynamic behavior of the structure and make them less efficient for high-resolution applications.
Innovation Solution
The proposed circuitry for digital-to-analog conversion uses a weighting resistor circuit with a first, second, and third resistive sub-circuit, where the resistivity of the second sub-circuit is equal to or smaller than the first, allowing for efficient scaling with fewer unit resistors, reducing silicon area and parasitic capacitance, and improving dynamic behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional resistor-based DACs use a big range of resistor values for high resolution, then conversion precision is improved, but physical dimension and device complexity increase
Solution Approach 1:
The weighting resistor circuit is divided into three separate resistive sub-circuits, each handling different portions of the digital input bits. This segmentation allows each sub-circuit to use resistors of more comparable values rather than requiring a wide range from small to large values, reducing the overall area while maintaining high resolution capability.
Solution Approach 2:
The patent introduces an intermediate node dimension in the circuit architecture, creating a multi-stage conversion path. Instead of direct resistor weighting from digital to analog output, the intermediate node allows for staged conversion, enabling high precision without requiring extreme resistor value ranges that would consume excessive area.
2Measurement precision
If conventional DACs use many resistors for high resolution, then conversion precision is improved, but parasitic nodes increase altering dynamic behavior
Solution Approach 1:
By segmenting the resistor network into three sub-circuits with hierarchical weighting, the patent reduces the total number of resistors required compared to conventional approaches. Fewer resistors directly translate to fewer parasitic nodes and simplified dynamic behavior while preserving high resolution through the staged conversion architecture.
3Measurement precision
If conventional DACs use different implementations of weighting resistors for different bit significance, then conversion precision is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Each of the three resistive sub-circuits is designed with localized weighting characteristics appropriate for its specific bit range. This allows each sub-circuit to be optimized independently with resistors of similar, manageable values, simplifying manufacturing while achieving the required precision through the combined effect of all three sub-circuits.
Data Source
AI summary
Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.