Segmented Resistor DAC Layout for Lower DNL, INL, and Settling Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters face challenges with differential nonlinearity (DNL), settling time, and integral nonlinearity (INL) due to resistor mismatch and switch resistance, which affect conversion accuracy and speed.
Innovation Solution
The implementation of a resistor network-based digital-to-analog converter (DAC) with specific switch configurations and resistor arrangements, such as series-connected resistors in parallel, and separate n-wells for resistors, reduces DNL and INL by minimizing resistor mismatch and optimizing settling time without increasing switch size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional resistor network is used in the DAC, then the device complexity is low, but the manufacturing precision deteriorates due to resistor mismatch causing DNL and INL errors
Solution Approach 1:
The resistor network is divided into multiple segments where each segment contains resistors with identical geometric dimensions. This segmentation ensures that resistors within each segment have matched characteristics, reducing mismatch errors. The DAC architecture partitions the resistor network into first and second segments, with each segment handling specific bit weights, thereby improving DNL and INL performance through localized matching.
Solution Approach 2:
Resistors within each segment are designed with identical local geometric properties (width, length, layout) to ensure uniform resistance values. This local quality control minimizes variation among resistors in the same segment, directly reducing DNL and INL errors caused by manufacturing tolerances.
2Manufacturing precision
If larger switches are used to reduce switch resistance, then the DNL and INL performance improves, but the device area increases
Solution Approach 1:
The switch network is segmented into multiple switches, each controlling a specific segment of the resistor network. This allows the use of smaller individual switches instead of one large switch, reducing overall device area while maintaining low on-resistance through parallel configuration. The segmented approach enables precise control of threshold voltages with compact switch elements.
Solution Approach 2:
Multiple smaller switches are combined in parallel to achieve the equivalent electrical performance of a single large switch. The segmented switches work together to control the resistor network, providing low on-resistance and accurate threshold voltage control without requiring large individual switch areas.
3Manufacturing precision
If the resistor network is optimized for accuracy, then the DNL and INL performance improves, but the settling time increases
Solution Approach 1:
The resistor network is segmented into multiple independent sections, each with controlled resistance values. This segmentation allows for optimized RC time constants in each segment, enabling faster settling while maintaining accuracy. The segmented architecture reduces the overall settling time by allowing independent charging/discharging of each segment rather than requiring the entire network to settle simultaneously.
Solution Approach 2:
The resistance values and geometric dimensions of resistors in different segments are optimized to achieve desired threshold voltage steps while controlling settling behavior. By adjusting resistor parameters (width, length, material) in each segment, the design achieves a balance between accuracy (DNL/INL) and speed (settling time) through parameter optimization.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) having a resistor network. The resistor network includes a first and second segments. The first segment includes a first switch coupled between a first supply voltage node and a first set of resistors. The second segment includes a second switch coupled between the first supply voltage node and a second set of resistors. The first segment includes a third switch coupled in series with a second resistor. The series-combination of the third switch and second resistor coupled in parallel with at least one resistor of the first set of resistors. The second segment includes a fourth switch coupled in series with a third resistor. The series-combination of the fourth switch and third resistor is coupled in parallel with at least one resistor of the second set of resistors.