Segmented Results Bus for Multi-Slice Processor Instruction Routing
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Solution Overview
Problem
Current computer processors face inefficiencies in terms of speed and power consumption, particularly in data centers and mobile devices, due to the complexity of managing multiple instructions and data operations across various slices within the processor.
Innovation Solution
A multi-slice processor architecture is introduced, featuring execution slices and load/store slices connected via a results bus with segmented bus lines, allowing for efficient instruction management by storing and retrieving identifiers and results within specific segments, thereby reducing power consumption through targeted snooping and data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-slice processor architecture is used to improve processing efficiency, then productivity is improved, but device complexity increases
Solution Approach 1:
The processor is divided into multiple execution slices and load/store slices, each capable of independent operation. The results bus is segmented into multiple segments, with each segment dedicated to carrying results of a specific instruction type. This segmentation allows parallel processing across slices while organizing data flow systematically, improving productivity without overwhelming complexity.
Solution Approach 2:
The results bus acts as an intermediary communication channel between execution slices and load/store slices. By introducing this dedicated communication infrastructure with segmented lines, the patent enables efficient data exchange without requiring complex direct interconnections between all processor components, thus improving productivity while managing device complexity.
2Use of energy by moving object
If selective snooping of identifier segments is implemented to reduce power consumption, then use of energy is improved, but device complexity increases
Solution Approach 1:
Different segments of the results bus are assigned to carry results of different instruction types. Each slice snoops only the identifier segment relevant to its instruction type rather than monitoring all segments. This local quality approach allows slices to focus their snooping efforts on specific segments, reducing power consumption while the segmented structure itself manages the complexity of selective monitoring.
Solution Approach 2:
Instead of requiring every slice to snoop all identifier segments on the results bus, the patent implements partial action by having each slice monitor only the specific segment corresponding to its instruction type. This reduces the total number of comparisons performed across the system, lowering power consumption while the segmented bus architecture provides the framework for this selective monitoring.
3Speed
If identifier storage and snooping is implemented to improve instruction execution efficiency, then speed is improved, but use of energy increases
Solution Approach 1:
The results bus is segmented into multiple segments, with each segment dedicated to carrying results of a specific instruction type. Each execution slice snoops only the identifier segment relevant to its instruction type rather than monitoring all segments. This local quality approach allows slices to focus their snooping efforts on specific segments, reducing the total number of comparisons performed across the system. The reduced scope of snooping operations lowers power consumption while maintaining fast identification and execution of instructions through the segmented architecture.
Data Source
AI summary
Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.