Segmented Reverse Map Table for Secure VM Memory Access
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Solution Overview
Problem
Hypervisors in computing devices may fail to enforce proper memory access controls, leading to unauthorized access of virtual machines to incorrect memory areas, compromising data security and integrity.
Innovation Solution
Implement a segmented reverse map table (RMT) architecture that is split into non-contiguous portions, ensuring each segment corresponds to a specific range of physical addresses, and includes an RMT segment index and counter table to enforce secure memory access by virtual machines and I/O devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional contiguous reverse map table is used, then memory access control is simplified, but security against hypervisor failures is compromised and memory utilization in NUMA configurations is suboptimal
Solution Approach 1:
The reverse map table is divided into multiple non-contiguous segments distributed across different memory regions. Each segment contains entries for specific virtual machine memory ranges, allowing secure isolation of memory access controls while improving utilization in NUMA configurations by placing segments in memory nodes closer to processing units.
2Adaptability or versatility
If memory is allocated contiguously for reverse map table, then access speed is improved, but adaptability to NUMA memory node configurations is reduced
Solution Approach 1:
Different segments of the reverse map table are placed in different NUMA memory nodes based on their access patterns and the virtual machines they serve. Frequently accessed segments are positioned in memory nodes with faster access times, optimizing local performance while maintaining overall system adaptability to NUMA architectures.
Data Source
AI summary
A computing device comprises a processor, a table walker, and a memory storing a segmented reverse map table in multiple non-contiguous portions of the memory. The table walker is configured to translate a virtual memory address specified by a memory access request to a physical memory address associated with the virtual memory address; and provide a requester associated with the memory access request with access to the associated physical memory address in response to an indication at the reverse map table that the requester is authorized to access the associated physical memory address.