Segmented Re-Wiring Layout for High-Current Semiconductor Packaging

Solution Overview

Problem

Existing semiconductor devices face challenges in reducing electrical resistance as they are designed to handle higher current capacities, necessitating further improvements in wiring configurations.

Innovation Solution

The semiconductor device employs a re-wiring structure with larger conductive layers and terminals, including a first and second re-wiring portion, connected via electrodes and conductive bonding layers, to enhance electrical conductivity and reduce resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the area of the Cu re-wiring is increased to reduce electrical resistance, then the current capacity is improved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:

Improveelectrical resistanceVSAvoidwiring structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The re-wiring is divided into multiple segments (first re-wiring portion, second re-wiring portion, third re-wiring portion) with different cross-sectional areas. The first and third portions have larger cross-sectional areas for reduced resistance, while the second portion has a smaller cross-sectional area, creating a segmented structure that balances electrical performance with manufacturing feasibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the re-wiring are assigned different cross-sectional areas based on their functional requirements. The first re-wiring portion (area S1) and third re-wiring portion (area S3) have larger areas to reduce resistance in high-current regions, while the second re-wiring portion (area S2) has a smaller area where lower current flows, optimizing both electrical performance and material usage.

Inventive Principle:

Principle #3Local quality

2Reliability

If the Cu re-wiring area is increased to handle larger currents, then the current capacity is improved, but the manufacturing precision requirements become more stringent

Engineering Contradiction:

Improvecurrent capacityVSAvoidwiring dimension control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The re-wiring is divided into multiple segments (first re-wiring portion, second re-wiring portion, third re-wiring portion) with different cross-sectional areas. The first and third portions have larger cross-sectional areas for reduced resistance, while the second portion has a smaller cross-sectional area, creating a segmented structure that balances electrical performance with manufacturing feasibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the re-wiring are assigned different cross-sectional areas based on their functional requirements. The first re-wiring portion (area S1) and third re-wiring portion (area S3) have larger areas to reduce resistance in high-current regions, while the second re-wiring portion (area S2) has a smaller area where lower current flows, optimizing both electrical performance and material usage.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250343180A1Semiconductor device and method for manufacturing semiconductor device

Publication Date: 2025.11.06 ROHM CO LTD

AI summary

A semiconductor device includes a semiconductor element, an electrode on a first side in a thickness direction of the semiconductor element, a re-wiring connected to the electrode, a terminal connected to the re-wiring, and a conductive bonding layer connected to the terminal. The terminal includes a first terminal and a second terminal. The conductive bonding layer includes a first conductive bonding layer connected to the first terminal and a second conductive bonding layer connected to the second terminal. The area of the second terminal is greater than the area of the first terminal. The area of the second conductive bonding layer is greater than the area of the first conductive bonding layer.