Segmented Ring Bus for SoC Trace Multiplexing
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Solution Overview
Problem
Current systems for obtaining real-time trace information from multiple processors on an integrated circuit face challenges due to bandwidth limitations, hardware complexity, and inflexibility in connector placement, making it difficult to achieve high-speed tracing and scalability.
Innovation Solution
A segmented ring bus architecture with dynamically toggled trace output circuits allows for efficient transmission of trace information from multiple processors to peripheral I/O channels, enabling flexible wiring and modular design, allowing all processors to transmit trace information simultaneously without diminishing operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a separate peripheral I/O channel is provided for each processor to obtain trace information, then the number of processors that can be traced increases, but the number of required peripheral I/O channels increases proportionally, which is not practical due to bandwidth limitations
Solution Approach 1:
Multiple processors share a common peripheral I/O channel through a ring bus architecture. The ring bus allows trace information from multiple processors to be multiplexed and transmitted through a single I/O channel, eliminating the need for separate channels for each processor while maintaining the ability to trace all processors.
Solution Approach 2:
A ring bus is introduced as an intermediary between processors and the peripheral I/O channel. The ring bus collects trace information from multiple processors and manages the transmission to the I/O channel, acting as a mediator that resolves the conflict between multiple data sources and a limited number of output channels.
2Device complexity
If multiple processors share a single peripheral I/O channel, then the number of required I/O channels decreases, but the operating frequency of the tracing mechanism decreases due to increased bus load
Solution Approach 1:
The ring bus is divided into multiple segments, with each segment serving a subset of processors. This segmentation reduces the load on any single segment, allowing trace information to be transmitted at higher frequencies without overwhelming the bus. Each segment operates semi-independently, improving overall system speed.
Solution Approach 2:
The ring bus implements periodic transmission of trace information from different processors in a round-robin or scheduled manner. This periodic action prevents any single processor from monopolizing the bus and maintains a high average operating frequency by ensuring fair and efficient utilization of the shared channel.
3Quantity of substance
If the number of processors on an SoC increases, then the tracing capability covers more processors, but the amount of hardware required for tracing increases, making the circuit more complex
Solution Approach 1:
The ring bus architecture provides a universal tracing mechanism that can accommodate any number of processors without requiring additional hardware components. The same ring bus structure serves both as the interconnection network and as the trace collection mechanism, eliminating the need for separate dedicated trace hardware for each processor.
Solution Approach 2:
The tracing system is designed to be dynamically scalable. As the number of processors increases, the ring bus automatically adapts by incorporating new processors into the existing structure without requiring fundamental changes to the hardware architecture. This dynamic nature allows the system to scale efficiently from a small number of processors to hundreds or thousands.
4Ease of manufacture
If peripheral I/O channels are limited by connector placement and wiring regions, then manufacturing cost and design flexibility are constrained, but the number of processors that can be traced is limited
Solution Approach 1:
The ring bus acts as an intermediary that decouples the physical location of processors from the location of peripheral I/O channels. Trace information can be collected from processors located anywhere on the chip and routed through the ring bus to I/O channels at convenient locations, eliminating the constraint that each processor must have a nearby I/O channel.
Solution Approach 2:
The ring bus introduces an additional dimensional aspect to the tracing architecture by creating a logical collection network that spans the entire chip. This allows trace information to be aggregated from distributed processors and transmitted through a centralized or distributed I/O interface, separating the spatial constraints of processor placement from I/O channel placement.
Data Source
AI summary
An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment. Each trace output circuit is configured to transmit trace information to a respective peripheral I/O channel when in the enabled state. Each trace output circuit is configured to transmit trace information to the adjacent downstream segment when in the disabled state.