Segmented Floating SCR Structure for Lower ESD Trigger Voltage
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Solution Overview
Problem
Integrated circuits are vulnerable to damage from random electrostatic discharge (ESD) events due to the limitations of existing silicon-controlled rectifier (SCR) structures in effectively managing ESD currents, particularly in terms of trigger and holding currents.
Innovation Solution
A structure for a silicon-controlled rectifier is designed with a specific configuration of wells and doped regions in a semiconductor substrate, including shallow trench isolation regions, to create a fully-isolated bidirectional device that reduces the trigger voltage while maintaining the failure current, featuring doped regions that are electrically floating and positioned between shallow trench isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SCR structure is used, then device simplicity is maintained, but trigger voltage is too high and ESD protection effectiveness is reduced
Solution Approach 1:
The patent divides the floating region into multiple segments (first floating region, second floating region, third floating region) separated by isolation regions. This segmentation allows independent optimization of each region's doping concentration and geometry, enabling reduced trigger voltage while maintaining device functionality. The segmented structure provides multiple current paths that can be independently controlled to achieve lower trigger voltage thresholds.
Solution Approach 2:
The patent applies different doping concentrations and geometries to different floating regions. The first floating region has a first doping concentration while the second floating region has a second doping concentration, creating local quality variations. This allows specific regions to be optimized for trigger voltage reduction while other regions maintain structural integrity and device stability.
2Speed
If trigger voltage is reduced, then ESD protection responsiveness is improved, but thermal breakdown risk increases
Solution Approach 1:
By segmenting the floating region into multiple regions with different doping concentrations, the patent creates multiple current paths with different activation characteristics. This segmentation allows the device to respond quickly to ESD events through the lower-voltage paths while the other paths provide thermal stability and prevent runaway conduction.
Solution Approach 2:
The patent changes the doping concentration parameter across different floating regions. The first floating region has a first doping concentration and the second floating region has a second doping concentration, creating a gradient that enables low trigger voltage response while maintaining thermal stability through the doping variation.
3Power
If floating region is made larger, then current conduction capability is improved, but device area increases
Solution Approach 1:
The floating region is segmented into multiple smaller regions (first, second, and third floating regions) rather than one large continuous region. This segmentation achieves the required current conduction capability through multiple parallel paths while reducing the overall device area compared to a single large floating region.
Solution Approach 2:
The patent creates vertical stacking of floating regions at different heights or levels within the device structure. By utilizing the vertical dimension, the patent achieves increased current conduction capability without proportionally increasing the planar device area, as the floating regions are positioned at different vertical levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively directs ESD currents away from sensitive devices, reducing the risk of damage by lowering the trigger voltage without compromising the failure current, thus enhancing the protection of integrated circuits from electrostatic discharge events.
Implementation Method 1
The first segment and the second segment of the third doped region are positioned between a first shallow trench isolation region and a second shallow trench isolation region... the first segment and the second segment each include a first portion that extends from the first shallow trench isolation region to the interface
Implementation Method 2
a protection device of the protection circuit is triggered to enter a low-impedance state that conducts the ESD current to ground and thereby shunts the ESD current away from the sensitive devices of the integrated circuit
Implementation Method 3
The first segment and the second segment of the third doped region are positioned between a first shallow trench isolation region and a second shallow trench isolation region in the semiconductor substrate
Data Source
Figure 1
Figure 2
Figure 2A
AI summary
Structures for a silicon-controlled rectifier and methods of forming same. The structure comprises a first well, a second well, and a third well in a semiconductor substrate. The third well is positioned between the first well and the second well. A first terminal includes a first doped region in the first well, and a second terminal includes a second doped region in the second well. The first well, the second well, and the second doped region have a first conductivity type, and the third well and the first doped region have a second conductivity type opposite to the first conductivity type. The structure further comprises a third doped region in the third well. The third doped region includes a first segment and a second segment, and the first segment is separated from the second segment by a portion of the first well and a portion of the third well.