Segmented Sealing Ring for Crack Prevention in Chip Packages
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Solution Overview
Problem
Wafer level packaging technologies face challenges in reducing the probability of cracks during the cutting process, which are exacerbated by the area occupied by sealing rings, leading to a reduction in the number of dies formed on the wafer.
Innovation Solution
A sealing ring structure comprising metal strips disposed between conductive pads, with at least one outside and one inside gap to form a curved channel that redirects stress away from the chip, preventing cracks and optimizing the use of wafer space by minimizing the width of the sealing ring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sealing ring is disposed between each chip to prevent cracks during cutting, then chip package reliability is improved, but the amount of dies formed on the wafer is reduced due to the extra area occupied by the sealing ring
Solution Approach 1:
The sealing ring is segmented into multiple discontinuous metal strips rather than forming a continuous ring. This segmentation reduces the total area occupied by the sealing structure while maintaining the crack prevention function, as the metal strips are strategically positioned to intercept crack propagation paths without requiring a complete circular barrier.
Solution Approach 2:
The sealing function is extracted from the traditional continuous ring structure and implemented through discrete metal strips positioned only where needed between conductive pads. This extraction allows the sealing function to be achieved with minimal material and area, eliminating the need for a complete circular sealing ring that would occupy excessive wafer space.
2Reliability
If a sealing ring is disposed between each chip to enhance chip package reliability, then crack prevention is improved, but the sealing ring occupies an extra area of the wafer
Solution Approach 1:
The sealing ring is divided into multiple discrete metal strips positioned between adjacent conductive pads. This segmentation reduces the total area occupied by the sealing structure from a complete circular ring to only the necessary segments between pads, minimizing wafer space consumption while maintaining crack interception capability.
Solution Approach 2:
The sealing structure is applied locally only where needed - specifically between adjacent conductive pads where crack propagation is most likely to occur. This localized approach concentrates the sealing function in critical areas rather than distributing it uniformly around the entire chip periphery, thereby reducing overall area occupation.
Data Source
AI summary
A chip package is provided. The chip package includes a chip, having a plurality of conductive pads disposed along a periphery of the chip, wherein the conductive pads have a width. A seal ring includes a plurality of metal strips disposed within a space between the two adjacent conductive pads. Each metal strip is electrically connected to at most one of the two adjacent conductive pads.