Segmented Search Memory Mat for Low-Power CAM

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Solution Overview

Problem

Conventional content addressable memory (CAM) devices face challenges in reducing power consumption while maintaining high-speed search performance, as they require accessing the entire memory space during search operations, leading to complex circuit configurations and increased power consumption.

Innovation Solution

The semiconductor device separates the search memory mat into multiple regions, divides key data into pieces, and writes entry addresses into separate memories, allowing for partial activation during searches, thereby reducing power consumption and maintaining high-speed search performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the entire memory space is accessed during search operations, then high-speed search performance is achieved, but power consumption increases significantly

Engineering Contradiction:
Improvesearch speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by stationary object

Solution Approach 1:

The search memory mat is divided into multiple separate memories (first separate memory, second separate memory, etc.), each storing a portion of the key data. During search operations, only the relevant separate memories need to be accessed, rather than the entire memory space, thus reducing power consumption while maintaining search speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of accessing the entire memory space during search, the system accesses only the necessary partial portions (specific separate memories) containing the relevant key data, thereby reducing energy consumption while maintaining adequate search performance.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If the entire memory space is accessed during search operations, then complete data search is ensured, but circuit configuration becomes complex

Engineering Contradiction:
Improvedata search completenessVSAvoidcircuit configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory space is segmented into multiple independent separate memories, each handling a specific portion of key data. This segmentation simplifies the circuit configuration by allowing independent access to smaller memory units rather than managing a single large complex memory space.

Inventive Principle:
Principle #1Segmentation

3Use of energy by stationary object

If key data is stored in separate memories, then power consumption is reduced, but memory access time may increase

Engineering Contradiction:
Improvepower consumptionVSAvoidmemory access time
Core Design Contradiction:
Use of energy by stationary objectVSLoss of time

Solution Approach 1:

By dividing key data into separate memories, the system can access only the necessary segments in parallel, reducing the overall access time compared to sequentially scanning an entire large memory space, while also reducing power consumption.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9240237B2Semiconductor device and method of writing/reading entry address into/from semiconductor device
Publication Date: 2016.01.19 NAGASE & CO LTD
  • US9240237B2 patent drawing
  • US9240237B2 patent drawing
  • US9240237B2 patent drawing

AI summary

The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.