Segmented Seed Layer Structure for High-Aspect Via Filling

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Solution Overview

Problem

The increasing aspect ratio of conductive vias in semiconductor packaging poses challenges in terms of reliability and process time, as they struggle to meet current and future requirements due to voids and disconnection issues.

Innovation Solution

A seed layer structure with neighboring sections spaced by a gap within a specific ratio (0.01% to 0.1%) in the carrier substrate, with an auxiliary seed layer added when the gap exceeds 0.1 μm to ensure complete filling of the conductive element, enhancing reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the density of electronic units mounted on the substrate is increased to improve device performance, then the device performance is improved, but the aspect ratio of conductive vias increases leading to reliability issues and process time increase

Engineering Contradiction:
Improvedevice performanceVSAvoidconductive via reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The seed layer is divided into multiple sections (first seed layer section, second seed layer section, and third seed layer section) separated by gaps. This segmentation allows each section to be independently formed and controlled, enabling better filling of high aspect ratio vias while maintaining electrical connectivity through the conductive element that bridges these sections.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the aspect ratio of conductive vias increases due to higher mounting density, then more electronic units can be mounted, but voids and disconnection issues occur in the conductive elements

Engineering Contradiction:
Improvemounting densityVSAvoidconductive element filling quality
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The seed layer structure with multiple sections and gaps is formed in advance before the conductive element deposition. This preliminary action prepares the substrate surface in a way that facilitates complete and void-free filling of the conductive element during subsequent electroplating or CVD processes, ensuring high manufacturing precision even for high aspect ratio vias.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Different sections of the seed layer are positioned at specific locations within the via (e.g., bottom section, middle section, top section), providing localized nucleation sites for conductive element growth. This local quality variation ensures uniform deposition and complete filling throughout the high aspect ratio via, preventing voids and disconnections.

Inventive Principle:
Principle #3Local quality

3Reliability

If a continuous seed layer is formed in high aspect ratio vias, then electrical connectivity is achieved, but the filling process becomes difficult and defects increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidconductive element filling process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The seed layer is segmented into multiple sections with gaps between them, which simplifies the formation process compared to attempting to form a continuous seed layer in high aspect ratio vias. The gaps allow better access for deposition processes and enable more controlled formation of each seed layer section, making the overall manufacturing easier while still achieving electrical connectivity through the bridging conductive element.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250316600A1Electronic device and method for manufacturing the same
Publication Date: 2025.10.09 INNOLUX CORP
  • US20250316600A1 patent drawing
  • US20250316600A1 patent drawing
  • US20250316600A1 patent drawing

AI summary

The present disclosure provides an electronic device and a method for manufacturing the same. The electronic device includes a carrier substrate having a first thickness in a first direction, a through-hole penetrating the carrier substrate, a seed layer structure disposed on the carrier substrate and extending into the through-hole, a conductive element disposed in the through-hole, and a circuit structure disposed on the conductive element. The seed layer structure includes a plurality of seed layers. A first seed layer among the plurality of seed layers includes two neighboring sections having a first gap in the first direction of the carrier substrate in which a ratio of the first gap to the first thickness ranges from 0.01% to 0.1%.