Segmented Source Drain Select Lines for 3D NAND Memory Erase Control

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Solution Overview

Problem

Three-dimensional NAND memory structures increase memory density but result in larger erasable block sizes, leading to inconvenient or intolerable increases in the number of simultaneously erasable pages, which is not desirable in many applications.

Innovation Solution

The solution involves segmenting global source and drain select lines within each physical block to create smaller erasable sub-blocks, with segmented drain select lines corresponding to segmented source lines, and designing junctions with different breakdown voltages to prevent erase disturb in adjacent non-selected sub-blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensional NAND memory structures are used to increase memory density, then storage capacity is improved, but erasable block size increases leading to inconvenient or intolerable increases in the number of simultaneously erasable pages

Engineering Contradiction:
Improvememory densityVSAvoiderasable block size
Core Design Contradiction:
Quantity of substanceVSEase of operation

Solution Approach 1:

The memory block is divided into multiple sub-blocks, each with its own segmented source and drain select lines. This segmentation allows the memory to be erased in smaller, more manageable units rather than requiring erasure of the entire large block, thus resolving the contradiction between maintaining high density and reducing erasable block size for ease of operation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of segmented source and drain select lines, allowing flexible selection and erasure of specific sub-blocks as needed. This dynamic capability enables the system to adapt erasure operations to actual needs, maintaining high density while providing operational flexibility comparable to smaller block sizes

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If segmented source and drain select lines are used to create smaller erasable sub-blocks, then erasable block size is reduced, but device complexity increases

Engineering Contradiction:
Improveerasable block sizeVSAvoidselect line segmentation
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent extends the select line structure into the vertical dimension with multiple tiers of segmented source and drain select lines. This three-dimensional arrangement allows for complex sub-block segmentation without proportionally increasing planar complexity, as the segmentation is organized across multiple levels rather than requiring extensive lateral routing

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If junctions with different breakdown voltages are designed to prevent erase disturb, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveerase disturb preventionVSAvoidjunction breakdown voltage control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements different breakdown voltage characteristics at different locations within the memory structure by designing first and second junctions with asymmetric dopant profiles. This local differentiation allows specific junctions to have tailored electrical properties that prevent erase disturb in non-selected sub-blocks, with the asymmetric doping providing inherent robustness against manufacturing variations

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for smaller erasable block sizes while maintaining high memory density, preventing unintended erasure of memory cells in non-selected sub-blocks during an erase operation, thus addressing the issue of increased block size in 3D memory arrays.

Implementation Method 1

Each of the drain select devices has an asymmetric dopant profile. The asymmetric dopant profile is configured to prevent an erase disturb of non-selected ones of the sub-blocks during an erase operation.

Methodology Applied
Scientific EffectBreakdown voltage: Avalanche Breakdown

Data Source

PatentUS10490279B2Erasable block segmentation for memory
Publication Date: 2019.11.26 MICRON TECHNOLOGY INC
  • US10490279B2 patent drawing
  • US10490279B2 patent drawing
  • US10490279B2 patent drawing

AI summary

Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.