Segmented Parallel-to-Serial Converter for Low-Power Data Shifting
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Solution Overview
Problem
Existing parallel-to-serial converters face high power consumption and latency issues, limiting their efficiency in converting parallel data to serial data, especially in applications like DDR-DRAM semiconductor memories.
Innovation Solution
The converter employs a method of loading segments of parallel data into a shift register and using multiple multiplexers to select and shift out the data in series, allowing for efficient loading and shifting of data without significant latency, supporting multiple word widths and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single multiplexer is used for parallel loading of an entire N-bit word into a shift register, then the device complexity is reduced, but the power consumption increases
Solution Approach 1:
The patent divides the N-bit parallel data into multiple segments (e.g., first segment, second segment, third segment) and processes them separately through the shift register. This segmentation allows the use of multiple smaller multiplexers instead of one large multiplexer, reducing overall power consumption while maintaining functionality. Each multiplexer handles a portion of the data, enabling more efficient power management.
Solution Approach 2:
The patent employs dynamic control signals (pload, sclk, muxsel) that enable the shift register and multiplexers to operate in different modes as needed. The system can dynamically switch between loading different segments and shifting out data, optimizing power consumption by activating only the necessary components at each stage of the conversion process.
2Loss of time
If a simple controllable shift register is used for parallel-to-serial conversion, then the latency is reduced, but the power consumption increases
Solution Approach 1:
By segmenting the parallel data into multiple groups that can be loaded and shifted in an interleaved manner, the patent reduces the total conversion time. While maintaining low latency through efficient segment processing, the system consumes less power by activating multiplexers and shift register stages only when needed, rather than continuously operating a simple shift register.
Solution Approach 2:
The patent loads multiple segments into the shift register in advance before the complete conversion is needed. This preliminary loading of segments allows the system to maintain a pipeline of data ready for serial output, reducing latency while managing power consumption through controlled activation of loading and shifting operations.
3Device complexity
If a fixed-size shift register is used, then the device complexity is reduced, but the adaptability to multiple word widths is limited
Solution Approach 1:
The patent segments the parallel data into multiple portions that can be flexibly configured to match different word widths. By using multiple multiplexers that can select and process different segment sizes, the system adapts to various input widths (e.g., 8-bit, 16-bit, 32-bit) without requiring a completely different shift register size, maintaining reasonable device complexity while achieving versatility.
Solution Approach 2:
The patent creates a universal parallel-to-serial converter that can handle multiple word widths through the combination of segmented data processing and controllable multiplexers. The same basic architecture (shift register with multiplexer control) serves multiple functions by adjusting segment configuration and control signals, eliminating the need for multiple dedicated converters for different word sizes.
Data Source
AI summary
A method for converting parallel data having a certain word size to serial data, comprises the steps of: loading a first segment of a word of the parallel data into a shift register having a first size, and inputting remaining segments of the word into two or more multiplexers connected in series for selecting a next segment of the word; selecting the next segment of the word to load into the shift register; shifting out the loaded segment of the word in the shift register as serial data output; loading the selected next segment of the word into the shift register; and repeating the selecting, shifting, and loading the next segment steps until all the remaining segments of the word have been shifted as serial data output.