Segmented Select Gate Source Lines for 3D Memory Capacitive Load Reduction
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Solution Overview
Problem
The increased block sizes and corresponding capacitive and resistive loads in three-dimensional memory implementations pose challenges for efficient memory operations, particularly during read and program operations, leading to design constraints and performance issues.
Innovation Solution
The implementation of segmented Select Gate Source (SGS) lines, which selectively enable SGS switches across memory subblocks, reducing capacitive loading during operations by controlling the number of active SGS switches, thereby optimizing memory access line voltages and reducing overall capacitive load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory implementation is used to improve memory cell density, then storage capacity increases, but capacitive and resistive loads increase
Solution Approach 1:
The SGS control lines are divided into multiple segmented lines, each controlling a specific subset of memory subblocks. This segmentation allows selective activation of only the SGS switches in subblocks containing selected strings during read/program operations, rather than activating all SGS switches across the entire memory block. Consequently, the total capacitive load is reduced proportionally to the fraction of active subblocks, directly resolving the contradiction between high density and manageable capacitive loading.
2Quantity of substance
If three-dimensional memory implementation is used to improve memory cell density, then storage capacity increases, but resistive loads increase
Solution Approach 1:
By segmenting the SGS control lines and selectively enabling only the necessary SGS switches in subblocks containing selected strings, the patent reduces the total number of simultaneously active switches. This decreases the overall resistive load in the memory block during operations, as fewer switch resistances are in parallel, thereby resolving the contradiction between increased density and manageable resistive loads.
3Adaptability or versatility
If all SGS switches are enabled during read operations, then all memory subblocks are accessible, but capacitive loading increases and performance decreases
Solution Approach 1:
The SGS control lines are segmented to provide independent control over different subblock groups. During read operations, only the SGS switches in subblocks containing the selected string are enabled, while switches in other subblocks remain disabled. This selective activation maintains full accessibility to all memory subblocks when needed, while simultaneously reducing capacitive loading to only the necessary subset, thereby improving operation speed without sacrificing adaptability.
Solution Approach 2:
The patent implements dynamic control of SGS switch activation based on the specific read or program operation being performed. The control circuit selectively enables SGS switches only in subblocks containing selected strings, adapting the active switch configuration to the current operation requirements. This dynamic approach reduces unnecessary capacitive loading while maintaining full memory accessibility, resolving the contradiction between versatility and performance.
Data Source
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Figure 3a~3b
AI summary
Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.