Segmented Silicon Interposer Packaging to Prevent Warping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Silicon interposers in 2.5D packaging are prone to warping and rupture due to thinning, and the integration level of chips and interposers needs improvement.
Innovation Solution
A chip packaging method involving the formation of multiple types of silicon interposer plates with varying conductive connection structures, cutting these plates into blocks, and fixing them on substrates with specific orientations to accommodate different chip specifications, followed by interconnecting the chips to these blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the silicon interposer is thinned to reduce package thickness, then the package becomes thinner, but the silicon interposer is prone to warp or rupture
Solution Approach 1:
The patent divides the silicon interposer into multiple independent blocks (first silicon interposer block, second silicon interposer block, etc.) with different thicknesses. This segmentation allows each block to be optimized independently - thinner blocks where needed to reduce overall package thickness, and thicker blocks where structural support is required to prevent warping and rupture.
Solution Approach 2:
Different regions of the silicon interposer structure are given different thicknesses and properties. Specifically, certain areas have thinner silicon interposer blocks to reduce package thickness, while other areas have thicker blocks to maintain structural integrity and prevent warping. This local differentiation resolves the contradiction between thinning and reliability.
2Adaptability or versatility
If multiple chips are connected to the silicon interposer to improve integration, then the integration level increases, but the silicon interposer is more prone to warping due to increased complexity
Solution Approach 1:
The silicon interposer is segmented into multiple blocks that can be selectively connected to different chips. This allows the integration of multiple chips with varying specifications while maintaining stability through the distributed block structure, where each block provides localized support and reduces overall warping stress.
Solution Approach 2:
The patent creates a dynamic configuration where different silicon interposer blocks can be selectively connected to different chips based on their specifications. This dynamic adaptability allows the system to accommodate varying chip requirements while maintaining structural stability through the modular block architecture.
3Ease of manufacture
If uniform silicon interposer blocks are used for all chips, then manufacturing is simplified, but chips with different specifications cannot be properly accommodated
Solution Approach 1:
The silicon interposer is divided into multiple blocks with different thicknesses and configurations. This segmentation enables the system to accommodate chips with different specifications by selecting appropriate blocks, while still maintaining relatively simple manufacturing processes through standardized block formation techniques.
Solution Approach 2:
The multiple silicon interposer blocks serve universal functions - they can be selectively connected to different chips with varying specifications. This multi-functionality allows a single set of block types to accommodate diverse chip requirements, achieving versatility without requiring completely different manufacturing processes for each chip type.
Data Source
AI summary
A chip packaging method and chip packaging structure are provided. The method includes: providing a substrate, a plurality of silicon wafers, and a plurality of chips; forming a plurality of sets of conductive connection structures on the plurality of silicon wafers respectively to form a plurality of silicon interposer plates; where at least one of the plurality of silicon interposer plates is different from other silicon interposer plates of the plurality of silicon interposer plates; cutting the plurality of silicon interposer plates respectively to obtain a plurality of silicon interposer blocks; selecting a plurality of target silicon interposer blocks from the plurality of silicon interposer blocks, and fixing the plurality of target silicon interposer blocks on the substrate; and interconnecting and arranging the plurality of chips on corresponding target silicon interposer blocks of the plurality of target silicon interposer blocks respectively.