Segmented Silicon Stressor Layers for Carrier Mobility
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Solution Overview
Problem
Current semiconductor integrated circuit (IC) fabrication methods face challenges in enhancing carrier mobility and device performance, particularly in reducing atomic forces that interfere with electron movement, which affects chip performance and energy consumption.
Innovation Solution
The method involves forming a metal-oxide-semiconductor (MOS) device using a process that includes forming a gate stack, lightly-doped drain and source regions, gate spacers, source and drain recesses, and stressors, with a cyclic deposition and etching process for epitaxial silicon layers, followed by hydrogen termination of the stressor surfaces to reduce dangling bonds and prevent condensation defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained silicon is used to enhance carrier mobility, then device performance is improved, but atomic forces interfering with electron movement are not sufficiently reduced
Solution Approach 1:
The source/drain stressor is segmented into multiple silicon-containing layers with different compositions and strains. Each layer is designed to provide specific strain characteristics, collectively reducing atomic forces more effectively than a single uniform layer while maintaining enhanced carrier mobility and device performance.
2Reliability
If multiple silicon-containing layers are formed in source/drain recesses, then carrier mobility is enhanced, but fabrication process complexity increases
Solution Approach 1:
The fabrication process employs periodic cyclic deposition and etching operations to form multiple silicon-containing layers. This periodic action allows systematic creation of complex multi-layer structures through repeated application of standardized deposition and pattern removal steps, making the complex fabrication process more controllable and repeatable.
Solution Approach 2:
Different silicon-containing layers are formed by changing deposition parameters such as gas flow rates, pressure, and temperature during cyclic PECVD processes. These parameter changes enable precise control over layer composition, thickness, and strain characteristics, achieving enhanced carrier mobility through systematic parameter optimization rather than complex structural design.
3Reliability
If hydrogen termination is applied to stressor surfaces, then dangling bonds are reduced and condensation defects are prevented, but additional processing steps are required
Solution Approach 1:
Hydrogen termination is applied as a preliminary action immediately after forming each silicon-containing layer. This preliminary hydrogenation prevents dangling bonds and condensation defects from forming in the first place, eliminating the need for subsequent defect repair steps and actually simplifying the overall process by preventing problems before they occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and device performance by reducing atomic forces, leading to better chip performance and lower energy consumption, while also minimizing thermal budget and reducing contamination risks through periodic purging and hydrogen treatment.
Implementation Method 1
a first silicon-containing layer is deposited in the source and drain recesses
Implementation Method 2
a cyclic deposition and etching process for epitaxial silicon layers
Implementation Method 3
followed by hydrogen termination of the stressor surfaces to reduce dangling bonds and prevent condensation defects
Data Source
AI summary
A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.