CMOS Process Using Segmented SOI Substrates for Crystal Orientation
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Solution Overview
Problem
Existing processes for creating CMOS integrated electronic circuits with transistors of different crystal orientations are costly and complex, particularly when using dual-SOI substrates, and do not efficiently reduce electrical resistance in the on-state for both n-type and p-type transistors.
Innovation Solution
A process involving a substrate with a primary monocrystalline silicon layer and an initial insulating layer, where the primary substrate and initial active layer have different crystal orientations, allowing for selective etching and epitaxial growth to form additional active layers with specific orientations, separated by insulating layers, resulting in transistors with reduced electrical resistance and simplified design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-SOI substrates with two active layers of different crystal orientations are used, then transistors with reduced electrical resistance can be realized, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The substrate is divided into two distinct zones: a first zone with an initial active layer of first crystal orientation for pMOS transistors, and a second zone with an additional active layer of second crystal orientation for nMOS transistors. This segmentation allows each transistor type to have optimized crystal orientation while using a single unified substrate structure, avoiding the complexity of dual-SOI substrates.
Solution Approach 2:
Different crystal orientations are assigned to different zones of the same substrate based on the specific requirements of pMOS and nMOS transistors. The first zone has (110) orientation optimized for pMOS, while the second zone has (100) orientation optimized for nMOS, allowing local optimization without global complexity.
2Adaptability or versatility
If direct molecular bonding of (110) film to (100) substrate is used, then active zones with different orientations are obtained, but the process requires amorphization and recrystallization steps increasing manufacturing complexity
Solution Approach 1:
The substrate is pre-prepared with two zones having different crystal orientations before transistor fabrication begins. The first zone has (110) orientation and the second zone has (100) orientation, allowing subsequent transistor processing to proceed directly without requiring amorphization and recrystallization steps.
Solution Approach 2:
Instead of transforming a single orientation layer into multiple orientations through complex processes, the invention uses a substrate that already has multiple orientations copied from different crystal planes of the silicon wafer, eliminating the need for amorphization and recrystallization.
3Reliability
If selective etching and epitaxial growth are used to form additional active layers, then transistors with optimized crystal orientations are achieved, but the manufacturing process steps increase
Solution Approach 1:
The invention changes the crystal orientation parameter of the substrate in different zones to match the optimal requirements for pMOS and nMOS transistors. By selecting appropriate crystal planes during substrate preparation, the need for multiple etching and epitaxial growth cycles is reduced, improving fabrication efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the creation of CMOS circuits with reduced electrical resistance in both n-type and p-type transistors, compatible with SOI technology, while being economically viable and simplifying circuit design, using a commercially available single active layer substrate.
Implementation Method 1
forming by epitaxy in the second zone, starting from the exposed surface of the primary substrate, a stack which comprises a portion of temporary monocrystalline layer and a portion of additional active monocrystalline layer
Data Source
AI summary
A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each active zone is electrically insulated from a primary substrate of the circuit, so that the entire circuit is compatible with SOI technology.