Segmented Source/Drain Epitaxial Growth for Multi-Gate Transistors
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Solution Overview
Problem
Wide gate pitches in multi-gate field-effect transistors lead to underfilling of semiconductor material in cavities, degrading device performance, including reduced radio-frequency performance, increased contact resistance, and potential contact open issues.
Innovation Solution
A structure and method for forming a field-effect transistor with multiple gate structures and a source/drain region comprising multiple sections of semiconductor layers, where portions of the semiconductor body are positioned between these sections, allowing for epitaxial growth within smaller cavities to alleviate underfilling and enhance material filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wide gate pitch is used in multi-gate field-effect transistor, then device layout flexibility is improved, but semiconductor material underfilling in cavities occurs degrading device performance
Solution Approach 1:
The source/drain region is divided into multiple discrete sections (first section, second section, third section) separated by gate structures. This segmentation allows each cavity between sections to be independently filled with semiconductor material, ensuring complete filling even with wide gate pitches. The segmentation transforms a single large filling challenge into multiple smaller, manageable filling operations.
2Adaptability or versatility
If wide gate pitch is used, then transistor design flexibility is improved, but contact resistance increases and contact open issues occur
Solution Approach 1:
The source/drain region is segmented into multiple sections with intermediate semiconductor body portions positioned between them. This creates multiple contact pathways and reduces the distance each contact must bridge, thereby reducing contact resistance and eliminating contact open issues while maintaining design flexibility.
Solution Approach 2:
The intermediate semiconductor body portions positioned between the first, second, and third sections of the source/drain region act as intermediary elements. These intermediaries provide continuous semiconductor material pathways that reduce contact resistance and prevent contact opens, while allowing the gate structures to maintain their wide pitch configuration.
3Ease of manufacture
If epitaxial growth is performed in large cavities, then source and drain formation is simplified, but underfilling occurs degrading radio-frequency performance
Solution Approach 1:
The epitaxial growth process is applied to multiple smaller cavities between the gate structures rather than a single large cavity. Each small cavity can be completely filled with epitaxial semiconductor material, ensuring manufacturing precision. The segmented approach maintains ease of manufacture by using standard epitaxial growth processes on manageable-scale cavities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves filling of semiconductor material, reduces contact resistance, and enhances overall device performance by utilizing multiple cavities for epitaxial growth, effectively addressing underfilling issues in wide gate pitch transistors.
Implementation Method 1
Another approach is to epitaxially grow sections of a semiconductor material from regions of the semiconductor body to provide the source and drain. The semiconductor material may be in situ doped during epitaxial growth with either a p-type dopant or an n-type dopant.
Data Source
AI summary
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.


