Semiconductor Contact Structure With Segmented Source/Drain Epitaxy
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Solution Overview
Problem
As semiconductor devices such as fin field-effect transistors (FinFETs) scale down, they are negatively impacted by the short channel effect and increased source/drain electron tunneling, necessitating improved processing and manufacturing techniques to enhance their performance and efficiency.
Innovation Solution
The manufacturing process involves forming semiconductor device structures with specific layers and patterns, including the formation of fins, insulating materials, dielectric features, and sacrificial gate stacks, followed by precise etching and epitaxial feature formation to optimize channel and source/drain regions, which helps in reducing contact resistance and preventing unintended merging of source/drain epitaxial features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase functional density, then production efficiency and cost are improved, but short channel effect and source/drain electron tunneling increase negatively impacting device performance
Solution Approach 1:
The source and drain regions are segmented into multiple epitaxial features with different heights, creating a stepped structure that reduces electron tunneling while maintaining scaling benefits. The channel region is also segmented into multiple fins to increase effective channel area without increasing footprint.
Solution Approach 2:
The patent introduces vertical dimensionality by creating epitaxial features of different heights and multi-level dielectric structures. This vertical segmentation allows control of electron tunneling in the vertical direction while maintaining horizontal scaling for high functional density.
2Area of moving object
If geometry size is decreased to increase functional density, then more circuits fit per chip area, but processing complexity increases
Solution Approach 1:
Sacrificial gate stacks are formed preliminarily to define the precise locations and heights of epitaxial features before the actual epitaxial growth. This preliminary structuring simplifies subsequent processing steps by providing self-aligned templates for material deposition.
Solution Approach 2:
Sacrificial gate stacks serve as intermediary structures that temporarily occupy space during fabrication, enabling precise positioning of source/drain epitaxial features. These intermediaries are removed after serving their positioning function, simplifying the final device structure.
3Reliability
If source/drain epitaxial features are formed to reduce contact resistance, then device performance improves, but unintended merging of adjacent features may occur
Solution Approach 1:
Adjacent source/drain epitaxial features are segmented at different heights, with intermediate dielectric features positioned between them at elevated levels. This vertical segmentation prevents lateral merging while maintaining low contact resistance through direct metal contact at the lower epitaxial level.
Solution Approach 2:
Dielectric features serve as intermediary barriers positioned between adjacent source/drain epitaxial features. These intermediaries prevent unintended merging while allowing the epitaxial features to extend close enough for low-resistance contact with overlying metal interconnects.
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.