Segmented Source-Drain Regions for Integrated Circuit Scaling
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Solution Overview
Problem
Current multi-gate transistors face challenges in scaling down and reducing short channel effects while maintaining current control and gate length, which affects the performance and density of integrated circuit devices.
Innovation Solution
The semiconductor device features an active fin with a gate electrode and a semiconductor pattern having segments with varying widths and thicknesses, along with a trench structure formed using multiple etching processes, to enhance current control and reduce short channel effects, allowing for more efficient scaling and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are scaled down to increase density, then device density improves, but short channel effects worsen
Solution Approach 1:
The source/drain region is divided into multiple segments (first segment, second segment, third segment) with different cross-sectional areas along the channel direction. This segmentation allows each segment to contribute differently to current control, enabling better SCE suppression while maintaining high density through compact design.
Solution Approach 2:
Different segments of the source/drain region are assigned different geometric properties (cross-sectional areas). The first segment has a larger cross-sectional area for robust current conduction, while the second and third segments have smaller areas for enhanced gate control and SCE reduction. This local differentiation optimizes both density and reliability.
2Reliability
If gate length is increased to reduce short channel effects, then short channel effect control improves, but current control capability deteriorates
Solution Approach 1:
The source/drain region is segmented into multiple portions with varying cross-sectional areas. The first segment (closer to the channel) has a larger area for strong current drive, while subsequent segments have progressively smaller areas that extend the effective control region without increasing gate length, thereby maintaining current control while suppressing SCE.
Solution Approach 2:
Instead of extending gate length in one dimension, the invention utilizes the vertical and lateral dimensions by creating segments with different cross-sectional areas. This multi-dimensional approach allows enhanced SCE control through extended field effect without compromising current control capability.
3Ease of manufacture
If source/drain region is made uniform to simplify manufacturing, then ease of manufacture improves, but current control and short channel effect reduction deteriorate
Solution Approach 1:
The source/drain region is divided into multiple segments that can be formed through sequential processing steps. Each segment can be independently defined using etching and deposition processes, allowing precise control of geometry while maintaining manufacturing feasibility through standard semiconductor fabrication techniques.
Solution Approach 2:
Mandrel structures are formed beforehand to define the segments of the source/drain region. These mandrels serve as templates for subsequent etching and material deposition, enabling precise formation of the segmented structure before final source/drain material is deposited, thus facilitating complex geometry with manageable process steps.
Data Source
AI summary
Integrated circuit devices with source/drain regions including multiple segments and methods of forming the same are provided. The integrated circuit devices may include a gate structure on a substrate and a source/drain region in the substrate adjacent the gate structure. The source/drain region may include a sidewall including a plurality of curved sidewall sections.