Segmented SRAM I/O BIST for Dual-Mode Read Path Testing
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Solution Overview
Problem
Conventional BIST testing methods for SRAM arrays are inadequate in testing the entire read circuitry, particularly the sensing circuits and data paths to sub-array data outputs, which is critical for mission-critical applications requiring continuous testing.
Innovation Solution
A specialized BIST circuit is implemented to test both the data output ports and sub-array data output ports by generating dedicated test data patterns, using multiplexers and XOR gates to confirm proper operation in both read modes, without modifying the memory circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BIST testing methods are used for SRAM arrays, then the testing process is simple, but the testing coverage is insufficient particularly for sensing circuits and data paths to sub-array data outputs
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each with its own local read bit lines and sub-array data output ports. The BIST circuit independently tests each sub-array's read circuitry including sensing circuits and data paths, ensuring comprehensive coverage without requiring a single complex testing mechanism for the entire array.
Solution Approach 2:
The BIST circuit is designed to test multiple components simultaneously including data output ports, sub-array data output ports, sensing circuits, and data paths. By generating dedicated test data patterns and using multiplexers and XOR gates, the same BIST circuit performs diverse testing functions that would otherwise require separate testing mechanisms.
2Speed
If the memory array is segmented into sub-arrays with local read bit lines, then the read speed is improved, but the complexity of testing all data paths increases
Solution Approach 1:
The memory array is segmented into multiple sub-arrays with dedicated local read bit lines and sub-array data output ports. This segmentation enables parallel read operations improving speed, while the BIST circuit tests each segment independently through dedicated data paths, making the testing complexity manageable through modular organization.
Solution Approach 2:
Multiplexers are used as intermediaries to selectively connect different data paths (data output ports and sub-array data output ports) to the BIST circuit. XOR gates serve as mediators to compare test data with actual output data. These intermediary components enable comprehensive testing of multiple data paths without requiring separate testing circuits for each path.
3Measurement precision
If dedicated test data patterns are generated for comprehensive testing, then the testing accuracy is improved, but the test time increases
Solution Approach 1:
The BIST circuit generates dedicated test data patterns in advance before actual testing begins. These pre-generated test patterns are stored and then applied systematically to test various data paths and circuit components, ensuring comprehensive coverage without requiring complex real-time pattern generation during the test execution phase.
Data Source
AI summary
An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.