SRAM Array Segmentation for Reliable In-Memory Computation
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Solution Overview
Problem
In-memory computation circuits using SRAM arrays face data flip errors due to simultaneous parallel access during matrix vector multiplication, which compromises the accuracy of subsequent operations.
Innovation Solution
The SRAM array is segmented into sub-arrays, with each sub-array having a word line and local bit lines, and global bit lines are capacitively coupled to local bit lines to minimize data flip errors, using a row controller to actuate only one word line per sub-array and an ADC to convert the analog output voltage to a digital decision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous parallel access to multiple word lines is performed during matrix vector multiplication, then computation speed is improved, but data flip errors increase
Solution Approach 1:
The SRAM array is divided into multiple sub-arrays, with each sub-array having its own local bit lines. This segmentation allows the system to perform parallel access across sub-arrays while isolating the data flip error risk within individual sub-arrays, thereby maintaining high computation speed while improving reliability.
2Productivity
If multiple word lines are actuated simultaneously, then throughput is improved, but accuracy of compute operations deteriorates
Solution Approach 1:
The array is segmented into sub-arrays that can be independently accessed. This allows throughput to be maintained by activating multiple sub-arrays simultaneously, while the localized nature of each sub-array prevents accuracy degradation from propagating across the entire array.
Solution Approach 2:
Local bit lines act as intermediaries between the memory cells and global bit lines. By introducing this intermediate layer, the system can aggregate signals from multiple sub-arrays while maintaining signal integrity and accuracy, even when multiple word lines are actuated simultaneously.
3Device complexity
If standard SRAM array architecture is used, then device complexity is reduced, but data flip errors occur during parallel access
Solution Approach 1:
The SRAM array is divided into sub-arrays with local bit lines, adding only moderate structural complexity while dramatically improving data stability during parallel access operations.
Solution Approach 2:
The architecture introduces a hierarchical dimension with local bit lines at the sub-array level and global bit lines at the array level. This dimensional organization allows standard SRAM cells to be used while preventing data flip errors through the intermediate local bit line structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of data flip errors and enhances the accuracy of in-memory compute operations by averaging local bit line voltages across sub-arrays, improving the reliability of computational results.
Implementation Method 1
global bit lines are capacitively coupled to local bit lines to minimize data flip errors
Data Source
AI summary
An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.