Segmented SRAM Contacts Reduce Metallization Layers

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Solution Overview

Problem

Conventional memory chip formation requires multiple metallization layers and tall contact plugs, leading to increased parasitic capacitance and RC delay due to high device density in SRAM cells.

Innovation Solution

The integration of static random access memory (SRAM) and one-transistor dynamic random access memory (DRAM) cells on a single chip, utilizing a first metallization layer for local connections and reducing the number of metallization layers needed, with first-layer contacts that are physically isolated and vertically spaced from the metallization layer, and a capacitor in the inter-layer dielectric, allowing for reduced RC delay and compatibility with DRAM cell formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional SRAM cell formation is used with multiple metallization layers, then local interconnection is achieved, but the number of metallization layers increases and device complexity increases

Engineering Contradiction:
Improvelocal interconnectionVSAvoidnumber of metallization layers
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The contact structure is segmented into two distinct parts: a lower contact portion extending from the source/drain region into the first inter-layer dielectric, and an upper contact portion extending from the first metallization layer into the first inter-layer dielectric. These two portions are physically isolated from each other within the dielectric layer, eliminating the need for a single continuous tall contact plug while achieving the same electrical connection function.

Inventive Principle:
Principle #1Segmentation

2Reliability

If tall contact plugs are used to connect source/drain regions to metallization layers, then electrical connection is achieved, but contact length increases and parasitic capacitance increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The contact path is divided into two separate segments: the lower contact portion that connects the source/drain region to the first inter-layer dielectric, and the upper contact portion that connects the first metallization layer to the same dielectric layer. By physically isolating these segments within the dielectric, the total effective capacitance is reduced compared to a single continuous tall contact plug.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first inter-layer dielectric serves as an intermediary medium that hosts both the lower and upper contact portions. This dielectric layer acts as a mediator that allows the two contact portions to be physically separated while still achieving electrical connection through the dielectric, thereby reducing parasitic capacitance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If high device density is implemented in memory cells, then storage capacity increases, but parasitic capacitance increases due to tall contact plugs

Engineering Contradiction:
Improvedevice densityVSAvoidparasitic capacitance
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

By segmenting the contact structure into lower and upper portions that are physically isolated within the first inter-layer dielectric, the patent reduces the effective capacitance of each contact segment. This allows for higher device density without proportionally increasing total parasitic capacitance, as each segmented contact has lower individual capacitance compared to a single tall contact plug.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7514757B2Memory formation with reduced metallization layers
Publication Date: 2009.04.07 MOSAID TECH
  • US7514757B2 patent drawing
  • US7514757B2 patent drawing
  • US7514757B2 patent drawing

AI summary

A semiconductor structure includes a static random access memory (SRAM) cell comprising a first pull-up MOS device, a first pull-down MOS device and a first pass-gate MOS device, a first metallization layer, and an inter-layer dielectric (ILD) underlying the first metallization layer, wherein the ILD comprises an upper portion and a lower portion, a first first-layer contact in the lower portion of the ILD and connecting at least two of the first pull-up MOS device, the first pull-down MOS device and the first pass-gate MOS device. The first first-layer contact is physically isolated from second layer contacts in the upper portion of the ILD. The semiconductor structure further includes a second first-layer contact in the lower portion of the ILD, and a second-layer contact having at least a portion on the second first-layer contact, wherein the second layer contact electrically connects the second first-layer contact.