Segmented SRAM Power Rails for Standby Leakage Reduction
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Solution Overview
Problem
Traditional SRAM architectures face significant challenges in reducing standby leakage current, particularly from bitcell arrays, due to the dependence on power supply voltage, leading to high wake-up times and inefficiencies in deep sleep retention mode.
Innovation Solution
The proposed memory architecture segments power supply rails within decoder slices to form segmented power supply nodes, allowing for controlled operation modes that reduce leakage currents by lowering voltage while maintaining higher than retention voltage, and includes array power headers and retention headers to manage these modes effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power supply voltage is lowered to retention voltage to reduce leakage current, then standby leakage current is reduced, but read/write operations cannot be performed
Solution Approach 1:
The memory array is divided into multiple independently controllable segments, each with its own power supply header. This allows different segments to be in different power states simultaneously - some in retention mode for low leakage and others in full power mode for active operations.
Solution Approach 2:
The power supply voltage for each memory segment is made dynamically adjustable through power headers that can switch between retention voltage and full power supply voltage. This dynamic control enables the system to adapt between low leakage standby mode and full operational capability as needed.
2Loss of energy
If memory is kept in deep sleep retention mode to reduce leakage, then power consumption is reduced, but wake-up time increases significantly
Solution Approach 1:
By segmenting the memory array into multiple independently controllable segments with separate power headers, only the necessary segments need to be woken up from retention mode rather than the entire memory array. This significantly reduces wake-up time while maintaining low power consumption for inactive segments.
Solution Approach 2:
Different segments of the memory array can have different power states - some in retention mode and others in full power mode. This local differentiation allows the system to minimize overall wake-up time by only activating segments that are currently needed for operations.
3Device complexity
If all bitcells have common bitline pair and common power supply to simplify architecture, then device complexity is reduced, but leakage current cannot be controlled per segment
Solution Approach 1:
The common power supply is segmented into multiple independent power supply headers, each controlling a specific memory segment. This segmentation enables independent leakage current control for each segment while maintaining a relatively simple overall architecture that builds upon the common bitline structure.
Data Source
AI summary
A memory architecture for optimizing leakage currents in standby mode and a method thereof is disclosed. The memory architecture includes a plurality of memory segments configured to operate in one or more modes of operations. The plurality of memory segments includes a plurality of decoder slices. Each of the plurality of decoder slice includes a plurality of wordlines running in the row direction; at least one array power header configured for controlling leakage currents within each of the plurality of decoder slice in the row direction; and a retention header. Each of the plurality of power supply rails running in the column direction are segmented within one or more decoder slice to form one or more segmented power supply node.