Segmented Syndrome Decoder Circuit for Large Codewords
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Solution Overview
Problem
Conventional syndrome decoders require a large circuit area and significant power consumption due to the increasing number of message bits, making them less practical for large codewords.
Innovation Solution
The proposed syndrome decoder circuit includes a syndrome computation circuit, a weight correction circuit, and a data correction circuit, which generate correction masks for error correction using a reduced number of syndrome bits, thereby minimizing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of message bits increases in a conventional ECC syndrome decoder, then the error correction capability improves, but the circuit area becomes quite large
Solution Approach 1:
The message bits are divided into multiple groups, each group being processed by a separate weight correction circuit. The syndrome bits are also divided into multiple sets, with each set fed to corresponding weight correction circuits. This segmentation allows the decoder to handle large codewords by breaking down the monolithic processing into parallel smaller units, reducing the overall circuit area while maintaining error correction capability.
Solution Approach 2:
The patent transitions from a single-dimensional processing approach to a multi-dimensional parallel processing architecture. Multiple weight correction circuits operate simultaneously on different groups of message bits using different sets of syndrome bits, effectively adding a parallelism dimension to the decoding process. This dimensional change enables handling of larger codewords without proportionally increasing circuit area.
2Reliability
If the number of message bits increases in a conventional ECC syndrome decoder, then the error correction capability improves, but the time delay for error checking becomes significant
Solution Approach 1:
The decoding process is organized into periodic parallel operations where multiple weight correction circuits simultaneously process different groups of message bits. This periodic parallel action reduces the overall error checking time by performing multiple decoding operations concurrently rather than sequentially, thereby reducing time delay while maintaining comprehensive error correction capability.
Solution Approach 2:
The syndrome bits are pre-computed from the received codeword before being distributed to multiple weight correction circuits. This preliminary computation of syndrome bits enables the subsequent parallel processing stages to operate simultaneously without waiting for sequential syndrome calculation, reducing the overall error checking time delay.
3Reliability
If the number of message bits increases in a conventional ECC syndrome decoder, then the error correction capability improves, but the power consumption increases
Solution Approach 1:
The power consumption is reduced through segmentation by dividing the decoding workload across multiple weight correction circuits that process different groups of message bits. Each circuit consumes less power individually, and the overall power consumption is optimized by enabling only the necessary circuits based on the syndrome bit patterns, rather than activating a single large-scale processing unit.
Solution Approach 2:
The patent employs partial action by using only the necessary number of weight correction circuits and syndrome bit sets required for the specific error correction task. Not all circuits operate at full capacity simultaneously, and the system adapts the level of processing activity to the actual error conditions detected, thereby reducing unnecessary power consumption while maintaining adequate error correction capability.
Data Source
AI summary
The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X-1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.