Segmented TDC Architecture for Sub-Picosecond Resolution
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Solution Overview
Problem
Conventional digital phase-locked loops face challenges in achieving high-resolution time-to-digital converter (TDC) resolution without incurring power and matching penalties, which limits spectral purity and increases phase noise in wireless communication devices, especially for emerging gigabit per second wireless standards.
Innovation Solution
The proposed solution involves a combination of re-circulating time-to-digital converters (RTDC) and stochastic time-to-digital converters (STDC), where RTDC replicates delay elements to eliminate mismatch and STDC exploits process variations to achieve fine resolution, allowing for a dynamic range of 200 ps with resolutions better than 1 ps and additional bits, while minimizing power consumption and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If delay cells are sized up to reduce mismatch and variations, then TDC linearity and monotonicity improve, but power dissipation increases quadratically with resolution
Solution Approach 1:
The TDC is divided into multiple segments, each with its own delay line and comparator. This segmentation allows each segment to operate at lower power while collectively achieving the required resolution and linearity through coordinated operation of all segments.
Solution Approach 2:
The patent introduces a new dimension by using multiple delay lines operating in parallel rather than a single long delay line. This dimensional change from serial to parallel architecture enables achieving the same resolution with reduced power consumption in each individual delay line.
2Measurement precision
If conventional delay verniers or delay interpolation techniques are used to achieve sub-gate delay TDC resolution, then TDC resolution improves, but mismatch and variations along the TDC delay line introduce non-linearity and non-monotonicity
Solution Approach 1:
Multiple identical delay lines are created as copies of each other. Each delay line is independently designed and manufactured, then their outputs are combined. This copying approach ensures that mismatches in one delay line do not affect the others, maintaining overall linearity while achieving high resolution.
Solution Approach 2:
The outputs from multiple delay lines are merged together through a combination logic circuit. This merging process integrates the results from multiple independent delay lines, achieving sub-gate delay resolution while compensating for individual line variations and maintaining linearity.
3Stability of the object's composition
If TDC delay cells are sized up to reduce mismatch, then TDC behavior monotonicity improves, but the area overhead increases
Solution Approach 1:
The TDC architecture is segmented into multiple smaller delay lines rather than one large delay line. Each segment uses smaller delay cells that consume less area, while the collective operation of all segments maintains the required monotonicity and stability through their coordinated output combination.
Solution Approach 2:
The patent transitions from a single-dimension approach (one long delay line) to a multi-dimensional approach (multiple parallel delay lines). This dimensional change allows achieving the same monotonicity requirement with smaller individual cells and reduced total area through parallel processing.
Data Source
AI summary
Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.