Segmented TIM Layers for Multi-Chip Thermal Coupling Control

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Solution Overview

Problem

Conventional semiconductor packages face challenges in efficiently cooling high-performance chips due to insufficient thermal conductivity and thermal coupling between chips, leading to reduced operational reliability.

Innovation Solution

A semiconductor package design featuring a first thermal interface material (TIM) layer with lower thermal conductivity and second TIM layers with higher thermal conductivity, arranged to contact the chips and reduce thermal coupling, along with a heat dissipation device for efficient heat management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a single TIM layer with high thermal conductivity is used to cool the chips, then heat dissipation efficiency is improved, but thermal coupling between adjacent chips increases

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidthermal coupling between chips
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The TIM structure is segmented into multiple layers with different thermal conductivities. The first TIM layer has lower thermal conductivity to reduce thermal coupling between chips, while the second TIM layer has higher thermal conductivity to improve heat dissipation from each chip to the heat dissipation device, addressing both thermal management requirements simultaneously

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the TIM structure have different thermal conductivity properties tailored to local requirements. The first TIM layer provides thermal isolation between adjacent chips, while the second TIM layer provides efficient thermal conduction from each chip to the heat dissipation device, optimizing thermal performance locally

Inventive Principle:
Principle #3Local quality

2Reliability

If a single TIM layer with low thermal conductivity is used to reduce thermal coupling, then thermal coupling between chips is reduced, but heat dissipation efficiency decreases

Engineering Contradiction:
Improvethermal coupling between chipsVSAvoidheat dissipation efficiency
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The TIM is divided into functional segments: the first TIM layer segment provides thermal isolation with lower thermal conductivity, while the second TIM layer segment provides heat dissipation with higher thermal conductivity, resolving the contradiction between thermal isolation and heat dissipation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The TIM structure uses composite material layers with different thermal conductivity properties. The combination of low thermal conductivity material (first TIM layer) and high thermal conductivity material (second TIM layer) creates a composite thermal management system that achieves both thermal coupling reduction and efficient heat dissipation

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design enhances cooling efficiency by 8% and reduces thermal coupling by 4%, thereby increasing the operational reliability of the semiconductor package.

Implementation Method 1

Thermal conductivity of each of the second TIM layers is higher than that of the first TIM layer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

the first TIM layer is interposed between the second TIM layers

Methodology Applied
Scientific EffectThermal insulation: Thermal Insulation

Data Source

PatentUS12431403B2Semiconductor package including thermal interface material (TIM) layers on semiconductor chips
Publication Date: 2025.09.30 SAMSUNG ELECTRONICS CO LTD
  • US12431403B2 patent drawing
  • US12431403B2 patent drawing
  • US12431403B2 patent drawing

AI summary

A semiconductor package is provided. The semiconductor package includes first and second semiconductor chips mounted on an interposer structure, an insulating filler covering sides of the first and second semiconductor chips, a first thermal interface material (TIM) layer arranged on the insulating filler, and second TIM layers arranged on the first and second semiconductor chips. The thermal conductivity of each of the second TIM layers is higher than that of the first TIM layer and the first TIM layer is between the second TIM layers.