Segmented Transpose Buffer for Video Transform Modules

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Solution Overview

Problem

Existing hardware implementations of discrete cosine transforms (DCT) in video codecs, such as those used in HEVC, face challenges in achieving optimal chip area efficiency and throughput, particularly in mobile devices, due to limited memory read bandwidth and processing cycle constraints.

Innovation Solution

The proposed solution involves a transform module architecture with a first row transform stage, a transpose buffer, and a second column transform stage, where the transpose buffer is implemented as a ping-pong buffer to reduce its size and the time intermediate values are stored, allowing simultaneous operation of both stages and optimizing memory read bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a conventional transpose buffer is used to collect and store output from the first transform stage, then data transfer between stages is enabled, but the die area and memory read bandwidth requirements increase significantly

Engineering Contradiction:
Improvedata transfer capabilityVSAvoiddie area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The transpose buffer is segmented into multiple smaller buffers (e.g., four 8x4 buffers instead of one large buffer). This segmentation allows the buffer to be filled and emptied in smaller chunks, reducing the peak memory read bandwidth requirement while maintaining the same functional capability of transferring data between transform stages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic buffer management where buffers are filled and emptied in a time-varying manner rather than requiring a static large buffer to hold all data at once. The buffer size and access patterns are optimized dynamically based on the processing pipeline's needs, reducing the maximum die area required.

Inventive Principle:
Principle #15Dynamics

2Area of stationary object

If the transpose buffer size is reduced to minimize die area, then chip area efficiency improves, but the time intermediate values are stored decreases which may affect processing throughput

Engineering Contradiction:
Improvedie areaVSAvoidprocessing latency
Core Design Contradiction:
Area of stationary objectVSLoss of time

Solution Approach 1:

By segmenting the transpose buffer into multiple smaller buffers, the patent enables parallel filling and emptying operations. Multiple buffers can be filled simultaneously while others are being emptied, reducing the total storage time required and maintaining throughput despite smaller individual buffer sizes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent ensures continuous useful action by overlapping buffer filling and emptying operations. While one buffer is being filled with intermediate values, another buffer is simultaneously being emptied to the second transform stage, eliminating idle time and maintaining continuous data flow despite reduced buffer sizes.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If multiple processing engines are used to simultaneously operate on input values, then processing throughput increases, but the memory read bandwidth requirement increases proportionally

Engineering Contradiction:
Improveprocessing throughputVSAvoidmemory read bandwidth
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the data processing into smaller chunks that can be handled by multiple processing engines in parallel. Each engine works on a subset of the input data, and the segmented transpose buffer structure allows efficient distribution of data to these engines without requiring proportional increases in total memory bandwidth.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10356440B2Scalable transform hardware architecture with improved transpose buffer
Publication Date: 2019.07.16 QUALCOMM INC
  • US10356440B2 patent drawing
  • US10356440B2 patent drawing
  • US10356440B2 patent drawing

AI summary

As the quality and quantity of shared video content increases, video encoding standards and techniques are being developed and improved to reduce bandwidth consumption over telecommunication and other networks. One such technique for compressing videos involves transforming image data into an alternate, encoding-friendly domain (e.g., by a two-dimensional discrete cosine transform). Transform modules may be implemented to perform these transformations, which may occur during both video encoding and decoding processes. Provided are exemplary techniques for improving the efficiency and performance of transform module implementations.